diff options
| author | Patrice Chotard | 2018-02-07 10:44:49 +0100 |
|---|---|---|
| committer | Tom Rini | 2018-03-13 21:45:37 -0400 |
| commit | cd389c03f270636e581a16ba157e37b47ae75d93 (patch) | |
| tree | 4bcfa1952498893282fea75a2f169e3275d9b036 | |
| parent | 09b335a6753f5c6ad418ca5eb0cdc599857272cc (diff) | |
ARM: dts: stm32: Add timer support for STM32F7
Add missing timer node to enable timer5 for STM32F7 SoCs family
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
| -rw-r--r-- | arch/arm/dts/stm32f7-u-boot.dtsi | 8 | ||||
| -rw-r--r-- | arch/arm/dts/stm32f746.dtsi | 7 |
2 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi index 9a9e4e5f371..4a677192a2d 100644 --- a/arch/arm/dts/stm32f7-u-boot.dtsi +++ b/arch/arm/dts/stm32f7-u-boot.dtsi @@ -1,3 +1,11 @@ +/{ + soc { + timer5: timer@40000c00 { + u-boot,dm-pre-reloc; + }; + }; +}; + &pinctrl { usart1_pins_a: usart1@0 { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index 46d148eab2c..8c6fa133e0a 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -323,6 +323,13 @@ pinctrl-names = "default", "opendrain"; max-frequency = <48000000>; }; + + timer5: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; + }; }; }; |