diff options
| author | Eugen Hristev | 2020-07-01 10:44:21 +0300 |
|---|---|---|
| committer | Eugen Hristev | 2020-10-19 09:19:53 +0300 |
| commit | dc470834a1ea50749c19ebac2c34e0edb898ab18 (patch) | |
| tree | c217dfd4ad9c1be1421aa82957faba0c8cdf354e | |
| parent | dff39042543fbd660320f07156db40afe7d0851a (diff) | |
clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics
This SoC has the 5th divisor for the mck0 master clock.
Adapt the characteristics accordingly.
Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| -rw-r--r-- | drivers/clk/at91/sama7g5.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index b96937673be..c0d9271966d 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -189,13 +189,13 @@ static const struct clk_pll_layout pll_layout_divio = { /* MCK0 characteristics. */ static const struct clk_master_characteristics mck0_characteristics = { .output = { .min = 140000000, .max = 200000000 }, - .divisors = { 1, 2, 4, 3 }, + .divisors = { 1, 2, 4, 3, 5 }, .have_div3_pres = 1, }; /* MCK0 layout. */ static const struct clk_master_layout mck0_layout = { - .mask = 0x373, + .mask = 0x773, .pres_shift = 4, .offset = 0x28, }; |