x86: Fix device-tree indentation

With the use of a phandle we can outdent the device tree nodes a little.
Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

1 files changed, 73 insertions, 74 deletions

diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 6b176339aed..daeb168b65f 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -23,42 +23,41 @@
 
 #ifdef CONFIG_ROM_SIZE
 &rom {
-		filename = "u-boot.rom";
-		end-at-4gb;
-		sort-by-offset;
-		pad-byte = <0xff>;
-		size = <CONFIG_ROM_SIZE>;
+	filename = "u-boot.rom";
+	end-at-4gb;
+	sort-by-offset;
+	pad-byte = <0xff>;
+	size = <CONFIG_ROM_SIZE>;
 #ifdef CONFIG_HAVE_INTEL_ME
-		intel-descriptor {
-			filename = CONFIG_FLASH_DESCRIPTOR_FILE;
-		};
-		intel-me {
-			filename = CONFIG_INTEL_ME_FILE;
-		};
+	intel-descriptor {
+		filename = CONFIG_FLASH_DESCRIPTOR_FILE;
+	};
+	intel-me {
+		filename = CONFIG_INTEL_ME_FILE;
+	};
 #endif
 #ifdef CONFIG_TPL
-		u-boot-tpl-with-ucode-ptr {
-			offset = <CONFIG_TPL_TEXT_BASE>;
-		};
-		u-boot-tpl-dtb {
-		};
-		u-boot-spl {
-			offset = <CONFIG_SPL_TEXT_BASE>;
-		};
-		u-boot-spl-dtb {
-		};
-		u-boot {
-			offset = <CONFIG_SYS_TEXT_BASE>;
-		};
+	u-boot-tpl-with-ucode-ptr {
+		offset = <CONFIG_TPL_TEXT_BASE>;
+	};
+	u-boot-tpl-dtb {
+	};
+	u-boot-spl {
+		offset = <CONFIG_SPL_TEXT_BASE>;
+	};
+	u-boot-spl-dtb {
+	};
+	u-boot {
+		offset = <CONFIG_SYS_TEXT_BASE>;
+	};
 #elif defined(CONFIG_SPL)
-		u-boot-spl-with-ucode-ptr {
-			offset = <CONFIG_SPL_TEXT_BASE>;
-		};
-
-		u-boot-dtb-with-ucode2 {
-			type = "u-boot-dtb-with-ucode";
-		};
-		u-boot {
+	u-boot-spl-with-ucode-ptr {
+		offset = <CONFIG_SPL_TEXT_BASE>;
+	};
+	u-boot-dtb-with-ucode2 {
+		type = "u-boot-dtb-with-ucode";
+	};
+	u-boot {
 		/*
 		 * TODO(sjg@chromium.org):
 		 * Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But
@@ -68,67 +67,67 @@
 		 * We need a better solution, perhaps a separate Kconfig.
 		 */
 #if CONFIG_SYS_TEXT_BASE == 0x1110000
-			offset = <0xfff00000>;
+		offset = <0xfff00000>;
 #else
-			offset = <CONFIG_SYS_TEXT_BASE>;
+		offset = <CONFIG_SYS_TEXT_BASE>;
 #endif
-		};
+	};
 #else
-		u-boot-with-ucode-ptr {
-			offset = <CONFIG_SYS_TEXT_BASE>;
-		};
+	u-boot-with-ucode-ptr {
+		offset = <CONFIG_SYS_TEXT_BASE>;
+	};
 #endif
-		u-boot-dtb-with-ucode {
-		};
-		u-boot-ucode {
-			align = <16>;
-		};
+	u-boot-dtb-with-ucode {
+	};
+	u-boot-ucode {
+		align = <16>;
+	};
 #ifdef CONFIG_HAVE_MRC
-		intel-mrc {
-			offset = <CONFIG_X86_MRC_ADDR>;
-		};
+	intel-mrc {
+		offset = <CONFIG_X86_MRC_ADDR>;
+	};
 #endif
 #ifdef CONFIG_HAVE_FSP
-		intel-fsp {
-			filename = CONFIG_FSP_FILE;
-			offset = <CONFIG_FSP_ADDR>;
-		};
+	intel-fsp {
+		filename = CONFIG_FSP_FILE;
+		offset = <CONFIG_FSP_ADDR>;
+	};
 #endif
 #ifdef CONFIG_HAVE_CMC
-		intel-cmc {
-			filename = CONFIG_CMC_FILE;
-			offset = <CONFIG_CMC_ADDR>;
-		};
+	intel-cmc {
+		filename = CONFIG_CMC_FILE;
+		offset = <CONFIG_CMC_ADDR>;
+	};
 #endif
 #ifdef CONFIG_HAVE_VGA_BIOS
-		intel-vga {
-			filename = CONFIG_VGA_BIOS_FILE;
-			offset = <CONFIG_VGA_BIOS_ADDR>;
-		};
+	intel-vga {
+		filename = CONFIG_VGA_BIOS_FILE;
+		offset = <CONFIG_VGA_BIOS_ADDR>;
+	};
 #endif
 #ifdef CONFIG_HAVE_VBT
-		intel-vbt {
-			filename = CONFIG_VBT_FILE;
-			offset = <CONFIG_VBT_ADDR>;
-		};
+	intel-vbt {
+		filename = CONFIG_VBT_FILE;
+		offset = <CONFIG_VBT_ADDR>;
+	};
 #endif
 #ifdef CONFIG_HAVE_REFCODE
-		intel-refcode {
-			offset = <CONFIG_X86_REFCODE_ADDR>;
-		};
+	intel-refcode {
+		offset = <CONFIG_X86_REFCODE_ADDR>;
+	};
 #endif
 #ifdef CONFIG_TPL
-		x86-start16-tpl {
-			offset = <CONFIG_SYS_X86_START16>;
-		};
+	x86-start16-tpl {
+		offset = <CONFIG_SYS_X86_START16>;
+	};
 #elif defined(CONFIG_SPL)
-		x86-start16-spl {
-			offset = <CONFIG_SYS_X86_START16>;
-		};
+	x86-start16-spl {
+		offset = <CONFIG_SYS_X86_START16>;
+	};
 #else
-		x86-start16 {
-			offset = <CONFIG_SYS_X86_START16>;
-		};
+	x86-start16 {
+		offset = <CONFIG_SYS_X86_START16>;
+	};
 #endif
 };
 #endif