net: sh_eth: Add support SH7734 Ethernet device

SH7734 has one channel ethernet device.
This support 10/100/1000Base, and RMII/MII/GMII.
And this has the same structure as SH7763.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>

2 files changed, 74 insertions, 28 deletions

diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index d5ef29c8371..3657bd695f9 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -59,7 +59,7 @@ int sh_eth_send(struct eth_device *dev, void *packet, int len)
 	}
 
 	/* packet must be a 4 byte boundary */
-	if ((int)packet & (4 - 1)) {
+	if ((int)packet & 3) {
 		printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
 		ret = -EFAULT;
 		goto err;
@@ -138,7 +138,7 @@ int sh_eth_recv(struct eth_device *dev)
 static int sh_eth_reset(struct sh_eth_dev *eth)
 {
 	int port = eth->port;
-#if defined(CONFIG_CPU_SH7763)
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 	int ret = 0, i;
 
 	/* Start e-dmac transmitter and receiver */
@@ -208,7 +208,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 	/* Point the controller to the tx descriptor list. Must use physical
 	   addresses */
 	outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port));
-#if defined(CONFIG_CPU_SH7763)
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 	outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port));
 	outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
 	outl(0x01, TDFFR(port));/* Last discriptor bit */
@@ -276,7 +276,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 
 	/* Point the controller to the rx descriptor list */
 	outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port));
-#if defined(CONFIG_CPU_SH7763)
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 	outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port));
 	outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
 	outl(RDFFR_RDLF, RDFFR(port));
@@ -346,7 +346,8 @@ static int sh_eth_phy_config(struct sh_eth_dev *eth)
 	struct eth_device *dev = port_info->dev;
 	struct phy_device *phydev;
 
-	phydev = phy_connect(miiphy_get_dev_by_name(dev->name),
+	phydev = phy_connect(
+			miiphy_get_dev_by_name(dev->name),
 			port_info->phy_addr, dev, PHY_INTERFACE_MODE_MII);
 	port_info->phydev = phydev;
 	phy_config(phydev);
@@ -398,7 +399,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 	outl(APR_AP, APR(port));
 	outl(MPR_MP, MPR(port));
 #endif
-#if defined(CONFIG_CPU_SH7763)
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 	outl(TPAUSER_TPAUSE, TPAUSER(port));
 #elif defined(CONFIG_CPU_SH7757)
 	outl(TPAUSER_UNLIMITED, TPAUSER(port));
@@ -418,7 +419,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 	/* Set the transfer speed */
 	if (phy->speed == 100) {
 		printf(SHETHER_NAME ": 100Base/");
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 		outl(GECMR_100B, GECMR(port));
 #elif defined(CONFIG_CPU_SH7757)
 		outl(1, RTRATE(port));
@@ -427,7 +428,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 #endif
 	} else if (phy->speed == 10) {
 		printf(SHETHER_NAME ": 10Base/");
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 		outl(GECMR_10B, GECMR(port));
 #elif defined(CONFIG_CPU_SH7757)
 		outl(0, RTRATE(port));
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 27fde05bd60..475a9e154cb 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -188,13 +188,51 @@ struct sh_eth_dev {
 #define TPAUSER(port)	(BASE_IO_ADDR + 0x0164)
 #define MAHR(port)		(BASE_IO_ADDR + 0x01c0)
 #define MALR(port)		(BASE_IO_ADDR + 0x01c8)
+
+#elif defined(CONFIG_CPU_SH7734)
+#define BASE_IO_ADDR	0xFEE00000
+
+#define EDSR(port)		(BASE_IO_ADDR)
+
+#define TDLAR(port)		(BASE_IO_ADDR + 0x0010)
+#define TDFAR(port)		(BASE_IO_ADDR + 0x0014)
+#define TDFXR(port)		(BASE_IO_ADDR + 0x0018)
+#define TDFFR(port)		(BASE_IO_ADDR + 0x001c)
+#define RDLAR(port)		(BASE_IO_ADDR + 0x0030)
+#define RDFAR(port)		(BASE_IO_ADDR + 0x0034)
+#define RDFXR(port)		(BASE_IO_ADDR + 0x0038)
+#define RDFFR(port)		(BASE_IO_ADDR + 0x003c)
+
+#define EDMR(port)		(BASE_IO_ADDR + 0x0400)
+#define EDTRR(port)		(BASE_IO_ADDR + 0x0408)
+#define EDRRR(port)		(BASE_IO_ADDR + 0x0410)
+#define EESR(port)		(BASE_IO_ADDR + 0x0428)
+#define EESIPR(port)	(BASE_IO_ADDR + 0x0430)
+#define TRSCER(port)	(BASE_IO_ADDR + 0x0438)
+#define TFTR(port)		(BASE_IO_ADDR + 0x0448)
+#define FDR(port)		(BASE_IO_ADDR + 0x0450)
+#define RMCR(port)		(BASE_IO_ADDR + 0x0458)
+#define RPADIR(port)	(BASE_IO_ADDR + 0x0460)
+#define FCFTR(port)		(BASE_IO_ADDR + 0x0468)
+#define ECMR(port)		(BASE_IO_ADDR + 0x0500)
+#define RFLR(port)		(BASE_IO_ADDR + 0x0508)
+#define ECSIPR(port)	(BASE_IO_ADDR + 0x0518)
+#define PIR(port)		(BASE_IO_ADDR + 0x0520)
+#define PIPR(port)		(BASE_IO_ADDR + 0x052c)
+#define APR(port)		(BASE_IO_ADDR + 0x0554)
+#define MPR(port)		(BASE_IO_ADDR + 0x0558)
+#define TPAUSER(port)	(BASE_IO_ADDR + 0x0564)
+#define GECMR(port)		(BASE_IO_ADDR + 0x05b0)
+#define MAHR(port)		(BASE_IO_ADDR + 0x05C0)
+#define MALR(port)		(BASE_IO_ADDR + 0x05C8)
+
 #endif
 
 /*
  * Register's bits
  * Copy from Linux driver source code
  */
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 /* EDSR */
 enum EDSR_BIT {
 	EDSR_ENT = 0x01, EDSR_ENR = 0x02,
@@ -205,11 +243,11 @@ enum EDSR_BIT {
 /* EDMR */
 enum DMAC_M_BIT {
 	EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
-#ifdef CONFIG_CPU_SH7763
-	EDMR_SRST	= 0x03,
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+	EDMR_SRST	= 0x03, /* Receive/Send reset */
 	EMDR_DESC_R	= 0x30, /* Descriptor reserve size */
 	EDMR_EL		= 0x40, /* Litte endian */
-#elif defined(CONFIG_CPU_SH7757) ||defined (CONFIG_CPU_SH7724)
+#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7724)
 	EDMR_SRST	= 0x01,
 	EMDR_DESC_R	= 0x30, /* Descriptor reserve size */
 	EDMR_EL		= 0x40, /* Litte endian */
@@ -223,7 +261,7 @@ enum DMAC_M_BIT {
 
 /* EDTRR */
 enum DMAC_T_BIT {
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 	EDTRR_TRNS = 0x03,
 #else
 	EDTRR_TRNS = 0x01,
@@ -262,7 +300,8 @@ enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
 
 /* EESR */
 enum EESR_BIT {
-#ifndef CONFIG_CPU_SH7763
+
+#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
 	EESR_TWB  = 0x40000000,
 #else
 	EESR_TWB  = 0xC0000000,
@@ -272,14 +311,14 @@ enum EESR_BIT {
 #endif
 	EESR_TABT = 0x04000000,
 	EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
-#ifndef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
 	EESR_ADE  = 0x00800000,
 #endif
 	EESR_ECI  = 0x00400000,
 	EESR_FTC  = 0x00200000, EESR_TDE  = 0x00100000,
 	EESR_TFE  = 0x00080000, EESR_FRC  = 0x00040000,
 	EESR_RDE  = 0x00020000, EESR_RFE  = 0x00010000,
-#ifndef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7724) && !defined(CONFIG_CPU_SH7757)
 	EESR_CND  = 0x00000800,
 #endif
 	EESR_DLC  = 0x00000400,
@@ -291,7 +330,7 @@ enum EESR_BIT {
 };
 
 
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 # define TX_CHECK (EESR_TC1 | EESR_FTC)
 # define EESR_ERR_CHECK	(EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
 		| EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
@@ -352,7 +391,7 @@ enum FCFTR_BIT {
 /* Transfer descriptor bit */
 enum TD_STS_BIT {
 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757) \
-		|| defined(CONFIG_CPU_SH7724)
+		|| defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7734)
 	TD_TACT = 0x80000000,
 #else
 	TD_TACT = 0x7fffffff,
@@ -368,7 +407,7 @@ enum TD_STS_BIT {
 enum RECV_RST_BIT { RMCR_RST = 0x01, };
 /* ECMR */
 enum FELIC_MODE_BIT {
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 	ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000,
 	ECMR_RZPF = 0x00100000,
 #endif
@@ -383,7 +422,7 @@ enum FELIC_MODE_BIT {
 
 };
 
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 #define ECMR_CHG_DM	(ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
 						ECMR_TXF | ECMR_MCT)
 #elif CONFIG_CPU_SH7757
@@ -396,14 +435,14 @@ enum FELIC_MODE_BIT {
 
 /* ECSR */
 enum ECSR_STATUS_BIT {
-#ifndef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
 	ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
 #endif
 	ECSR_LCHNG = 0x04,
 	ECSR_MPD = 0x02, ECSR_ICD = 0x01,
 };
 
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
 #else
 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
@@ -412,14 +451,20 @@ enum ECSR_STATUS_BIT {
 
 /* ECSIPR */
 enum ECSIPR_STATUS_MASK_BIT {
-#ifndef CONFIG_CPU_SH7763
-	ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
-#endif
+#if defined(CONFIG_CPU_SH7724)
+	ECSIPR_PSRTOIP = 0x10,
+	ECSIPR_LCHNGIP = 0x04,
+	ECSIPR_ICDIP = 0x01,
+#elif defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+	ECSIPR_PSRTOIP = 0x10,
+	ECSIPR_PHYIP = 0x08,
 	ECSIPR_LCHNGIP = 0x04,
-	ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
+	ECSIPR_MPDIP = 0x02,
+	ECSIPR_ICDIP = 0x01,
+#endif
 };
 
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
 #else
 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
@@ -458,7 +503,7 @@ enum RPADIR_BIT {
 	RPADIR_PADR = 0x0003f,
 };
 
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 # define RPADIR_INIT (0x00)
 #else
 # define RPADIR_INIT (RPADIR_PADS1)