diff options
| author | Dario Binacchi | 2023-09-03 22:48:46 +0200 |
|---|---|---|
| committer | Patrice Chotard | 2023-10-04 13:26:02 +0200 |
| commit | f479f5dbb7ac1014c47fa5092acd9cd478e0bbf3 (patch) | |
| tree | bed4333b7f89adac7246e59ec6013d0937cb9746 | |
| parent | 5b9e395726b591f79a190e56e53a27b9c766efab (diff) | |
ARM: dts: stm32: add ltdc support on stm32f746 MCU
The patch applies the changes from Linux commit 008ef8b3a1a00 ("Add LTDC
(Lcd-tft Display Controller) support") and removes the same settings
from stm32f746-disco-u-boot.dtsi.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| -rw-r--r-- | arch/arm/dts/stm32f746-disco-u-boot.dtsi | 18 | ||||
| -rw-r--r-- | arch/arm/dts/stm32f746.dtsi | 10 |
2 files changed, 16 insertions, 12 deletions
diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi index 522cffb1ac9..3c2b9fc5951 100644 --- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi @@ -63,19 +63,13 @@ }; }; }; +}; - soc { - ltdc: display-controller@40016800 { - compatible = "st,stm32-ltdc"; - reg = <0x40016800 0x200>; - resets = <&rcc STM32F7_APB2_RESET(LTDC)>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>; - pinctrl-0 = <<dc_pins>; - - status = "okay"; - bootph-all; - }; - }; +<dc { + clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>; + pinctrl-0 = <<dc_pins>; + status = "okay"; + bootph-all; }; &fmc { diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index 7b4bd805c99..79dad3192e1 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -518,6 +518,16 @@ }; }; + ltdc: display-controller@40016800 { + compatible = "st,stm32-ltdc"; + reg = <0x40016800 0x200>; + interrupts = <88>, <89>; + resets = <&rcc STM32F7_APB2_RESET(LTDC)>; + clocks = <&rcc 1 CLK_LCD>; + clock-names = "lcd"; + status = "disabled"; + }; + pwrcfg: power-config@40007000 { compatible = "st,stm32-power-config", "syscon"; reg = <0x40007000 0x400>; |