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| author | Michal Simek | 2022-02-23 16:17:38 +0100 |
|---|---|---|
| committer | Michal Simek | 2022-03-07 16:33:47 +0100 |
| commit | 59e1bdd48d059563287a4424f3d6ef9218c49581 (patch) | |
| tree | 69e0c48348aeefe300530cc4603d5fbe08d18396 /MAINTAINERS | |
| parent | c36dc2449b1f902aed49548b4f058ec51ec42f08 (diff) | |
arm64: zynqmp: Setup clock for DP and DPDMA
Clocks are coming from shared HW design where these frequencies should be
aligned with PLL setup.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/04454c50d0d13e450976942085d763ab5aa38f98.1645629459.git.michal.simek@xilinx.com
Diffstat (limited to 'MAINTAINERS')
0 files changed, 0 insertions, 0 deletions