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| author | wdenk | 2004-08-01 23:02:45 +0000 |
|---|---|---|
| committer | wdenk | 2004-08-01 23:02:45 +0000 |
| commit | 9aea95307fdb0ffe0d3a98a17ac73e5040c9756a (patch) | |
| tree | 812e59d74bb6ab942f7c797b6bbcc5e7c2ad4a8f /MAINTAINERS | |
| parent | 281e00a3be453a169d854f824a460359d10f92bb (diff) | |
Patch by Jon Loeliger, 16 Jul 2004:
- support larger DDR memories up to 2G on the PC8540/8560ADS and
STXGP3 boards
- Made MPC8540/8560ADS be 33Mhz PCI by default.
- Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
and CONFIG_L2_INIT_RAM options.
- Refactor Local Bus initialization out of SDRAM setup.
- Re-implement new version of LBC11/DDR11 errata workarounds.
- Moved board specific PCI init parts out of CPU directory.
- Added TLB entry for PCI-1 IO Memory
- Updated README.mpc85xxads
Diffstat (limited to 'MAINTAINERS')
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