diff options
| author | Alexey Brodkin | 2015-03-30 13:36:04 +0300 |
|---|---|---|
| committer | Alexey Brodkin | 2015-04-03 09:47:50 +0300 |
| commit | 6eb15e50f48927c65a67371555b5afc24b3c7d21 (patch) | |
| tree | 0e6f7a560fece41ed04cfdd3fad6591433c56e19 /arch/arc/lib/start.S | |
| parent | 09424d11192cffd4793b7bc922c5b47d4fe88a4d (diff) | |
arc: add support for SLC (System Level Cache, AKA L2-cache)
ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache).
This change adds functions required for controlling SLC:
* slc_enable/disable
* slc_flush/invalidate
For now we just disable SLC to escape DMA coherency issues until either:
* SLC flush/invalidate is supported in DMA APIin U-Boot
* hardware DMA coherency is implemented (that might be board specific
so probably we'll need to have a separate Kconfig option for
controlling SLC explicitly)
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'arch/arc/lib/start.S')
| -rw-r--r-- | arch/arc/lib/start.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S index 48ee86e54ad..e1ef19cb889 100644 --- a/arch/arc/lib/start.S +++ b/arch/arc/lib/start.S @@ -18,6 +18,10 @@ ENTRY(_start) mov %fp, %sp /* Unconditionally disable caches */ +#ifdef CONFIG_ISA_ARCV2 + bl slc_flush + bl slc_disable +#endif bl flush_dcache_all bl dcache_disable bl icache_disable |