ARM: OMAP4+: Clean up the pmic code

The pmic code is duplicated for OMAP 4 and 5.
Instead move the data to Soc specific place and
share the code.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>

3 files changed, 70 insertions, 124 deletions

diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index 03651489588..40808d18ff0 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -27,7 +27,6 @@ LIB	=  $(obj)lib$(SOC).o
 
 COBJS	+= sdram_elpida.o
 COBJS	+= hwinit.o
-COBJS	+= clocks.o
 COBJS	+= emif.o
 COBJS	+= prcm-regs.o
 COBJS	+= hw_data.o
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
deleted file mode 100644
index 4772743947f..00000000000
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- *
- * Clock initialization for OMAP4
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Aneesh V <aneesh@ti.com>
- *
- * Based on previous work by:
- *	Santosh Shilimkar <santosh.shilimkar@ti.com>
- *	Rajendra Nayak <rnayak@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/omap_common.h>
-#include <asm/gpio.h>
-#include <asm/arch/clocks.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/utils.h>
-#include <asm/omap_gpio.h>
-
-#ifndef CONFIG_SPL_BUILD
-/*
- * printing to console doesn't work unless
- * this code is executed from SPL
- */
-#define printf(fmt, args...)
-#define puts(s)
-#endif /* !CONFIG_SPL_BUILD */
-
-/*
- * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
- * We set the maximum voltages allowed here because Smart-Reflex is not
- * enabled in bootloader. Voltage initialization in the kernel will set
- * these to the nominal values after enabling Smart-Reflex
- */
-void scale_vcores(void)
-{
-	u32 volt, omap_rev;
-
-	omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
-
-	omap_rev = omap_revision();
-
-	/*
-	 * Scale Voltage rails:
-	 * 1. VDD_CORE
-	 * 3. VDD_MPU
-	 * 3. VDD_IVA
-	 */
-	if (omap_rev < OMAP4460_ES1_0) {
-		/*
-		 * OMAP4430:
-		 * VDD_CORE = TWL6030 VCORE3
-		 * VDD_MPU = TWL6030 VCORE1
-		 * VDD_IVA = TWL6030 VCORE2
-		 */
-		volt = 1200;
-		do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
-
-		/*
-		 * note on VDD_MPU:
-		 * Setting a high voltage for Nitro mode as smart reflex is not
-		 * enabled. We use the maximum possible value in the AVS range
-		 * because the next higher voltage in the discrete range
-		 * (code >= 0b111010) is way too high.
-		 */
-		volt = 1325;
-		do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
-		volt = 1200;
-		do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
-
-	} else {
-		/*
-		 * OMAP4460:
-		 * VDD_CORE = TWL6030 VCORE1
-		 * VDD_MPU = TPS62361
-		 * VDD_IVA = TWL6030 VCORE2
-		 */
-		volt = 1200;
-		do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
-		/* TPS62361 */
-		volt = 1203;
-		do_scale_tps62361(TPS62361_VSEL0_GPIO,
-				  TPS62361_REG_ADDR_SET1, volt);
-		/* VCORE 2 - supplies vdd_iva */
-		volt = 1200;
-		do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
-	}
-}
-
-u32 get_offset_code(u32 offset)
-{
-	u32 offset_code, step = 12660; /* 12.66 mV represented in uV */
-
-	if (omap_revision() == OMAP4430_ES1_0)
-		offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
-	else
-		offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
-
-	offset_code = (offset + step - 1) / step;
-
-	/* The code starts at 1 not 0 */
-	return ++offset_code;
-}
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
index 6ae3986d733..18efa6c828a 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -30,12 +30,15 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/omap_common.h>
 #include <asm/arch/clocks.h>
+#include <asm/omap_gpio.h>
 #include <asm/io.h>
 
 struct prcm_regs const **prcm =
 			(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
 struct dplls const **dplls_data =
 			(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
+struct vcores_data const **omap_vcores =
+		(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
 
 /*
  * The M & N values in the following tables are created using the
@@ -194,6 +197,70 @@ struct dplls omap4460_dplls = {
 	.usb = usb_dpll_params_1920mhz
 };
 
+struct pmic_data twl6030_4430es1 = {
+	.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
+	.step = 12660, /* 10 mV represented in uV */
+	/* The code starts at 1 not 0 */
+	.start_code = 1,
+};
+
+struct pmic_data twl6030 = {
+	.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
+	.step = 12660, /* 10 mV represented in uV */
+	/* The code starts at 1 not 0 */
+	.start_code = 1,
+};
+
+struct pmic_data tps62361 = {
+	.base_offset = TPS62361_BASE_VOLT_MV,
+	.step = 10000, /* 10 mV represented in uV */
+	.start_code = 0,
+	.gpio = TPS62361_VSEL0_GPIO,
+	.gpio_en = 1
+};
+
+struct vcores_data omap4430_volts_es1 = {
+	.mpu.value = 1325,
+	.mpu.addr = SMPS_REG_ADDR_VCORE1,
+	.mpu.pmic = &twl6030_4430es1,
+
+	.core.value = 1200,
+	.core.addr = SMPS_REG_ADDR_VCORE3,
+	.core.pmic = &twl6030_4430es1,
+
+	.mm.value = 1200,
+	.mm.addr = SMPS_REG_ADDR_VCORE2,
+	.mm.pmic = &twl6030_4430es1,
+};
+
+struct vcores_data omap4430_volts = {
+	.mpu.value = 1325,
+	.mpu.addr = SMPS_REG_ADDR_VCORE1,
+	.mpu.pmic = &twl6030,
+
+	.core.value = 1200,
+	.core.addr = SMPS_REG_ADDR_VCORE3,
+	.core.pmic = &twl6030,
+
+	.mm.value = 1200,
+	.mm.addr = SMPS_REG_ADDR_VCORE2,
+	.mm.pmic = &twl6030,
+};
+
+struct vcores_data omap4460_volts = {
+	.mpu.value = 1203,
+	.mpu.addr = TPS62361_REG_ADDR_SET1,
+	.mpu.pmic = &tps62361,
+
+	.core.value = 1200,
+	.core.addr = SMPS_REG_ADDR_VCORE1,
+	.core.pmic = &tps62361,
+
+	.mm.value = 1200,
+	.mm.addr = SMPS_REG_ADDR_VCORE2,
+	.mm.pmic = &tps62361,
+};
+
 /*
  * Enable essential clock domains, modules and
  * do some additional special settings needed
@@ -382,6 +449,7 @@ void hw_data_init(void)
 
 	case OMAP4430_ES1_0:
 	*dplls_data = &omap4430_dplls_es1;
+	*omap_vcores = &omap4430_volts_es1;
 	break;
 
 	case OMAP4430_ES2_0:
@@ -389,11 +457,13 @@ void hw_data_init(void)
 	case OMAP4430_ES2_2:
 	case OMAP4430_ES2_3:
 	*dplls_data = &omap4430_dplls;
+	*omap_vcores = &omap4430_volts;
 	break;
 
 	case OMAP4460_ES1_0:
 	case OMAP4460_ES1_1:
 	*dplls_data = &omap4460_dplls;
+	*omap_vcores = &omap4460_volts;
 	break;
 
 	default: