diff options
| author | Lokesh Vutla | 2013-02-12 01:33:45 +0000 |
|---|---|---|
| committer | Tom Rini | 2013-03-11 11:06:11 -0400 |
| commit | d4d986ee27fe6a78e50d4789d5b08b87a5e64892 (patch) | |
| tree | 0bc6adb8e8d303a5512194a6f5cb4a426e678079 /arch/arm/cpu/armv7/omap5/prcm-regs.c | |
| parent | 9100edecf8379c357037c34044757202f85480b2 (diff) | |
ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup
After power-up SRCOMP cells are by-passed by default in OMAP5.
Software has to enable these SRCOMP sells.
For ES2: All 5 SRCOMP cells needs to be enabled.
For ES1: Only 4 SRCOMP cells in core power domain are enabled.
The 1 in wkup domain is not enabled because smart i/os
of wkup domain work with default compensation code.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap5/prcm-regs.c')
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/prcm-regs.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 58c9d5039a7..5e5abcce5be 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -149,6 +149,7 @@ struct prcm_regs const omap5_es1_prcm = { /* cm2.core */ .cm_coreaon_bandgap_clkctrl = 0x4a008648, + .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, .cm_l3_1_clkstctrl = 0x4a008700, .cm_l3_1_dynamicdep = 0x4a008708, .cm_l3_1_l3_1_clkctrl = 0x4a008720, @@ -294,6 +295,7 @@ struct prcm_regs const omap5_es1_prcm = { .cm_wkup_rtc_clkctrl = 0x4ae07880, .cm_wkup_bandgap_clkctrl = 0x4ae07888, .cm_wkupaon_scrm_clkctrl = 0x4ae07890, + .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898, .prm_vc_val_bypass = 0x4ae07ba0, .prm_vc_cfg_i2c_mode = 0x4ae07bb4, .prm_vc_cfg_i2c_clk = 0x4ae07bb8, @@ -502,7 +504,7 @@ struct prcm_regs const omap5_es2_prcm = { .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, .cm_coreaon_bandgap_clkctrl = 0x4a008648, - + .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, /* cm2.core */ .cm_l3_1_clkstctrl = 0x4a008700, @@ -650,6 +652,7 @@ struct prcm_regs const omap5_es2_prcm = { .cm_wkup_rtc_clkctrl = 0x4ae07980, .cm_wkup_bandgap_clkctrl = 0x4ae07988, .cm_wkupaon_scrm_clkctrl = 0x4ae07990, + .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998, .prm_vc_val_bypass = 0x4ae07ca0, .prm_vc_cfg_i2c_mode = 0x4ae07cb4, .prm_vc_cfg_i2c_clk = 0x4ae07cb8, |