diff options
| author | Simon Glass | 2017-04-05 17:53:18 -0600 |
|---|---|---|
| committer | Tom Rini | 2017-05-11 22:03:39 -0400 |
| commit | 6775a8208e3ac60f09b982c2d7b3258e0af86540 (patch) | |
| tree | 0769a9a7530e304cd65a5f661458d9036b788c67 /arch/arm/cpu/armv8/cache.S | |
| parent | f97cae95759efd4dbb19acdde201a1f13815832a (diff) | |
arm: Support cache invalidate
At present there is not operation to invalidate a cache range. This seems
to be needed to fill out the cache operations. Add an implementation based
on the flush operation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/cache.S')
| -rw-r--r-- | arch/arm/cpu/armv8/cache.S | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index f1deaa72302..7cba308ee7a 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -138,6 +138,30 @@ ENTRY(__asm_flush_dcache_range) dsb sy ret ENDPROC(__asm_flush_dcache_range) +/* + * void __asm_invalidate_dcache_range(start, end) + * + * invalidate data cache in the range + * + * x0: start address + * x1: end address + */ +ENTRY(__asm_invalidate_dcache_range) + mrs x3, ctr_el0 + ubfm x3, x3, #16, #19 + mov x2, #4 + lsl x2, x2, x3 /* cache line size */ + + /* x2 <- minimal cache line size in cache system */ + sub x3, x2, #1 + bic x0, x0, x3 +1: dc ivac, x0 /* invalidate data or unified cache */ + add x0, x0, x2 + cmp x0, x1 + b.lo 1b + dsb sy + ret +ENDPROC(__asm_invalidate_dcache_range) /* * void __asm_invalidate_icache_all(void) |