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author | Minkyu Kang | 2014-10-07 19:14:03 +0900 |
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committer | Minkyu Kang | 2014-10-07 19:14:03 +0900 |
commit | 3cc83f9d08a80fddf4c1e8e766eff8273f30814c (patch) | |
tree | 831246a1b77d26d0296a84c90684e0fee0368737 /arch/arm/cpu/armv8/fsl-lsch3/mp.h | |
parent | 64f41212d880f3d00c6994d973aadeec5bda1b65 (diff) | |
parent | 6dd0e7c00bfa5ce861a72b8e4a3ef9e787306125 (diff) |
Merge branch 'uboot'
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-lsch3/mp.h')
-rw-r--r-- | arch/arm/cpu/armv8/fsl-lsch3/mp.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.h b/arch/arm/cpu/armv8/fsl-lsch3/mp.h new file mode 100644 index 00000000000..06ac0bcf361 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.h @@ -0,0 +1,36 @@ +/* + * Copyright 2014, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_CH3_MP_H +#define _FSL_CH3_MP_H + +/* +* Each spin table element is defined as +* struct { +* uint64_t entry_addr; +* uint64_t status; +* uint64_t lpid; +* }; +* we pad this struct to 64 bytes so each entry is in its own cacheline +* the actual spin table is an array of these structures +*/ +#define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0 +#define SPIN_TABLE_ELEM_STATUS_IDX 1 +#define SPIN_TABLE_ELEM_LPID_IDX 2 +#define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */ +#define SPIN_TABLE_ELEM_SIZE 64 + +#define id_to_core(x) ((x & 3) | (x >> 6)) +#ifndef __ASSEMBLY__ +extern u64 __spin_table[]; +extern u64 *secondary_boot_code; +extern size_t __secondary_boot_code_size; +int fsl_lsch3_wake_seconday_cores(void); +void *get_spin_tbl_addr(void); +phys_addr_t determine_mp_bootpg(void); +void secondary_boot_func(void); +#endif +#endif /* _FSL_CH3_MP_H */ |