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authorWu, Josh2015-07-27 11:40:17 +0800
committerTom Rini2015-08-12 20:47:48 -0400
commit633b6ccedf9d536fd93299b2207a5227dedd987c (patch)
tree1fca53c6a3d3ed616fa172e68b2ae78c0b074d7a /arch/arm/cpu
parent387871a10edc777a5d94bfdbd6b86e493991826e (diff)
ARM: cache: implement a default weak flush_cache() function
Current many cpu use the same flush_cache() function, which just call the flush_dcache_range(). So implement a weak flush_cache() for all the cpus to use. In original weak flush_cache() in arch/arm/lib/cache.c, there has some code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache() function as well. That means the original code for ARM1136 & ARM926ejs in weak flush_cache() of arch/arm/lib/cache.c is totally useless. So in this patch remove such code in flush_cache() and only call flush_dcache_range(). Signed-off-by: Josh Wu <josh.wu@atmel.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/arm11/cpu.c9
-rw-r--r--arch/arm/cpu/arm926ejs/cache.c9
-rw-r--r--arch/arm/cpu/armv7/cache_v7.c13
-rw-r--r--arch/arm/cpu/armv8/cache_v8.c8
4 files changed, 0 insertions, 39 deletions
diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c
index 06dee0fc1b9..1e4c2142b13 100644
--- a/arch/arm/cpu/arm11/cpu.c
+++ b/arch/arm/cpu/arm11/cpu.c
@@ -110,11 +110,6 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
}
-void flush_cache(unsigned long start, unsigned long size)
-{
- flush_dcache_range(start, start + size);
-}
-
#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
void invalidate_dcache_all(void)
{
@@ -123,10 +118,6 @@ void invalidate_dcache_all(void)
void flush_dcache_all(void)
{
}
-
-void flush_cache(unsigned long start, unsigned long size)
-{
-}
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 99d1a139b0d..e5c1a6ae6c9 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -69,11 +69,6 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
}
-
-void flush_cache(unsigned long start, unsigned long size)
-{
- flush_dcache_range(start, start + size);
-}
#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
void invalidate_dcache_all(void)
{
@@ -82,10 +77,6 @@ void invalidate_dcache_all(void)
void flush_dcache_all(void)
{
}
-
-void flush_cache(unsigned long start, unsigned long size)
-{
-}
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
/*
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 4f0e4062a2d..a5aa4fa6436 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -286,15 +286,6 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop)
flush_dcache_range(start, stop);
v7_inval_tlb();
}
-
-/*
- * Flush range from all levels of d-cache/unified-cache used:
- * Affects the range [start, start + size - 1]
- */
-void flush_cache(unsigned long start, unsigned long size)
-{
- flush_dcache_range(start, start + size);
-}
#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
void invalidate_dcache_all(void)
{
@@ -308,10 +299,6 @@ void arm_init_before_mmu(void)
{
}
-void flush_cache(unsigned long start, unsigned long size)
-{
-}
-
void mmu_page_table_flush(unsigned long start, unsigned long stop)
{
}
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index cd160c4b633..835f6a6525e 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -253,11 +253,3 @@ void __weak enable_caches(void)
icache_enable();
dcache_enable();
}
-
-/*
- * Flush range from all levels of d-cache/unified-cache
- */
-void flush_cache(unsigned long start, unsigned long size)
-{
- flush_dcache_range(start, start + size);
-}