diff options
| author | Andre Przywara | 2022-07-13 16:27:58 +0100 |
|---|---|---|
| committer | Andre Przywara | 2023-01-21 01:32:23 +0000 |
| commit | 7f0938eac5d867b202d74b2a734ac3f924411bc9 (patch) | |
| tree | e521a0f8a7fc38890863b802476f600cf3942f34 /arch/arm/cpu | |
| parent | eb53e7743c8fde2ff6b47b54075086154b0126c1 (diff) | |
sunxi: fel: drop redundant "control register" save/restore
For some reasons shrouded in mystery, the code saving the FEL state was
saving the SCTLR register twice, with the second copy trying to justify
itself by using its ancient "control register" alias name.
Drop the redundant second copy, both from the fel_stash data structure,
and also the code saving and restoring it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/fel_utils.S | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/fel_utils.S b/arch/arm/cpu/armv7/sunxi/fel_utils.S index b2310751d9d..78bb1657fc1 100644 --- a/arch/arm/cpu/armv7/sunxi/fel_utils.S +++ b/arch/arm/cpu/armv7/sunxi/fel_utils.S @@ -20,8 +20,6 @@ ENTRY(save_boot_params) str lr, [r0, #12] mrc p15, 0, lr, c12, c0, 0 @ Read VBAR str lr, [r0, #16] - mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register - str lr, [r0, #20] b save_boot_params_ret ENDPROC(save_boot_params) @@ -29,8 +27,6 @@ ENTRY(return_to_fel) mov sp, r0 mov lr, r1 ldr r0, =fel_stash - ldr r1, [r0, #20] - mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register ldr r1, [r0, #16] mcr p15, 0, r1, c12, c0, 0 @ Write VBAR ldr r1, [r0, #12] |