diff options
| author | Fabio Estevam | 2014-01-16 10:57:29 -0200 |
|---|---|---|
| committer | Stefano Babic | 2014-01-17 10:16:48 +0100 |
| commit | be2a3bb39adf1fdd274fc427e30ef62eb86441a1 (patch) | |
| tree | 1ea4e8c9fcf3c57104754a05d2332c29b88026af /arch/arm/cpu | |
| parent | 3a21773129f6ef218f1978d05a1a5d5cf6801ab6 (diff) | |
mx6: Revert "mx6: soc: Disable VDDPU regulator"
Commit 022298278 (mx6: soc: Disable VDDPU regulator) is causing kernel hang
for people using FSL kernel 3.0.35 and 3.10, so revert it for now.
Reported-by: Otavio Salvador <otavio@ossystems.com.br>
Reported-by: Pierre Aubert <p.aubert@staubli.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 41 |
1 files changed, 0 insertions, 41 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 009a644abf2..0208cba9cc7 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -19,8 +19,6 @@ #include <asm/arch/mxc_hdmi.h> #include <asm/arch/crm_regs.h> -#define VDDPU_MASK (0x1f << 9) - enum ldo_reg { LDO_ARM, LDO_SOC, @@ -179,50 +177,11 @@ static void imx_set_wdog_powerdown(bool enable) writew(enable, &wdog2->wmcr); } -static void imx_set_vddpu_power_down(void) -{ - struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - struct gpc_regs *gpc = (struct gpc_regs *)GPC_BASE_ADDR; - - u32 reg; - - /* - * Disable the brown out detection since we are going to be - * disabling the LDO. - */ - reg = readl(&anatop->ana_misc2); - reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN; - writel(reg, &anatop->ana_misc2); - - /* need to power down xPU in GPC before turning off PU LDO */ - reg = readl(&gpc->gpu_ctrl); - writel(reg | 0x1, &gpc->gpu_ctrl); - - reg = readl(&gpc->ctrl); - writel(reg | 0x1, &gpc->ctrl); - while (readl(&gpc->ctrl) & 0x1) - ; - - /* Mask the ANATOP brown out interrupt in the GPC. */ - reg = readl(&gpc->imr4); - reg |= 0x80000000; - writel(reg, &gpc->imr4); - - /* disable VDDPU */ - writel(VDDPU_MASK, &anatop->reg_core_clr); - - /* Clear the BO interrupt in the ANATOP. */ - reg = readl(&anatop->ana_misc1); - reg |= 0x80000000; - writel(reg, &anatop->ana_misc1); -} - int arch_cpu_init(void) { init_aips(); imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ - imx_set_vddpu_power_down(); #ifdef CONFIG_APBH_DMA /* Start APBH DMA */ |