diff options
| author | Stefan Roese | 2013-06-14 10:55:00 +0200 |
|---|---|---|
| committer | Tom Rini | 2013-07-26 16:39:10 -0400 |
| commit | bf0e86606df37e3344b14d12e58aa8799a15fe37 (patch) | |
| tree | 921308c778d32bf05b651753731997f84606b92d /arch/arm/cpu | |
| parent | 8b485ba12b0defa0c4ed3559789250238f8331a8 (diff) | |
arm: omap3: spl: Fix problem with 8bit NAND devices
Currently in OMAP3 SPL, the GPMC for NAND is configured for 16bit
access. This patch adds support for 8bit NAND devices as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/omap3/mem.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c index 1832affa5bb..e6494096544 100644 --- a/arch/arm/cpu/armv7/omap3/mem.c +++ b/arch/arm/cpu/armv7/omap3/mem.c @@ -21,6 +21,17 @@ struct gpmc *gpmc_cfg; #if defined(CONFIG_CMD_NAND) +#if defined(GPMC_NAND_ECC_SP_x8_LAYOUT) || defined(GPMC_NAND_ECC_LP_x8_LAYOUT) +static const u32 gpmc_m_nand[GPMC_MAX_REG] = { + SMNAND_GPMC_CONFIG1, + SMNAND_GPMC_CONFIG2, + SMNAND_GPMC_CONFIG3, + SMNAND_GPMC_CONFIG4, + SMNAND_GPMC_CONFIG5, + SMNAND_GPMC_CONFIG6, + 0, +}; +#else static const u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, M_NAND_GPMC_CONFIG2, @@ -29,6 +40,7 @@ static const u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG5, M_NAND_GPMC_CONFIG6, 0 }; +#endif #endif /* CONFIG_CMD_NAND */ #if defined(CONFIG_CMD_ONENAND) |