arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN913x DB

This patch adds the dtsi/dts files needed to support the Marvell
Octeon TX2 CN913x DB. This is only the base port with not all
interfaces supported fully.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>

1 files changed, 166 insertions, 0 deletions

diff --git a/arch/arm/dts/cn9131-db.dtsi b/arch/arm/dts/cn9131-db.dtsi
new file mode 100644
index 00000000000..5057605584d
--- /dev/null
+++ b/arch/arm/dts/cn9131-db.dtsi
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018-2021 Marvell International Ltd.
+ */
+
+#undef CP110_NAME
+#undef CP110_NUM
+#undef CP110_PCIE_MEM_SIZE
+#undef CP110_PCIEx_CPU_MEM_BASE
+#undef CP110_PCIEx_BUS_MEM_BASE
+
+/* CP110-1 Settings */
+#define CP110_NAME			cp1
+#define CP110_NUM			1
+#define CP110_PCIE_MEM_SIZE(iface)	(0xf00000)
+#define CP110_PCIEx_CPU_MEM_BASE(iface)	(0xe2000000 + (iface) * 0x1000000)
+#define CP110_PCIEx_BUS_MEM_BASE(iface)	(CP110_PCIEx_CPU_MEM_BASE(iface))
+
+#include "armada-cp110.dtsi"
+
+/ {
+	model = "Marvell CN9131 development board";
+	compatible = "marvell,cn9131-db";
+
+	aliases {
+		gpio3 = &cp1_gpio0;
+		gpio4 = &cp1_gpio1;
+	};
+
+	cp1 {
+		config-space {
+			cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
+				compatible = "regulator-fixed";
+				pinctrl-names = "default";
+				pinctrl-0 = <&cp1_xhci0_vbus_pins>;
+				regulator-name = "cp1-xhci0-vbus";
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5000000>;
+				startup-delay-us = <100000>;
+				regulator-force-boot-off;
+				gpio = <&cp1_gpio0 3 GPIO_ACTIVE_HIGH>;
+			};
+			cp1_reg_usb3_current_lim0: cp1_usb3_current_limiter@0 {
+				compatible = "regulator-fixed";
+				regulator-min-microamp = <900000>;
+				regulator-max-microamp = <900000>;
+				regulator-force-boot-off;
+				gpio = <&cp1_gpio0 2 GPIO_ACTIVE_HIGH>;
+			};
+			cp1_pcie_reset_pins: cp1-pcie-reset-pins {
+				marvell,pins = <0>;
+				marvell,function = <0>;
+			};
+		};
+	};
+};
+
+&cp1_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp1_i2c0_pins>;
+	status = "okay";
+	clock-frequency = <100000>;
+};
+
+/* CON40 */
+&cp1_pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp1_pcie_reset_pins>;
+	marvell,reset-gpio = <&cp1_gpio0 0 GPIO_ACTIVE_LOW>;
+	status = "okay";
+	num-lanes = <2>;
+		/* non-prefetchable memory */
+	ranges = <0x82000000 0 0xe2000000 0 0xe2000000 0 0xf00000>;
+};
+
+&cp1_pinctl {
+	compatible = "marvell,mvebu-pinctrl",
+		     "marvell,cp115-standalone-pinctrl";
+	bank-name ="cp1-110";
+
+	/* MPP Bus:
+	 *	[0-12]	GPIO
+	 *	[13-16]	SPI1
+	 *	[17-27]	GPIO (Default)
+	 *	[28]	SATA1_PRESENT_ACTIVEn
+	 *	[29-34]	GPIO (Default)
+	 *	[35-36]	xSMI
+	 *	[37-38] I2C0
+	 *	[39-62]	GPIO
+	 */
+		/*   0    1    2    3    4    5    6    7    8    9 */
+	pin-func = < 0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
+		     0x0  0x0  0x0  0x3  0x3  0x3  0x3  0x0  0x0  0x0
+		     0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x9  0x0
+		     0x0  0x0  0x0  0x0  0x0  0x7  0x7  0x2  0x2  0x0
+		     0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
+		     0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
+		     0x0  0x0  0x0 >;
+
+	cp1_i2c0_pins: cp1-i2c-pins-0 {
+		marvell,pins = < 37 38 >;
+		marvell,function = <2>;
+	};
+	cp1_spi0_pins: cp1-spi-pins-0 {
+		marvell,pins = < 13 14 15 16 >;
+		marvell,function = <3>;
+	};
+	cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
+		marvell,pins = <3>;
+		marvell,function = <0>;
+	};
+};
+
+/* CON32 */
+&cp1_sata0 {
+	status = "okay";
+};
+
+/* U24 */
+&cp1_spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp1_spi0_pins>;
+	reg = <0x700680 0x50>,		/* control */
+	      <0x2000000 0x1000000>,	/* CS0 */
+	      <0 0xffffffff>,		/* CS1 */
+	      <0 0xffffffff>,		/* CS2 */
+	      <0 0xffffffff>;		/* CS3 */
+	status = "okay";
+
+	spi-flash@0 {
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		compatible = "jedec,spi-nor", "spi-flash";
+		reg = <0x0>;
+		/* On-board MUX does not allow higher frequencies */
+		spi-max-frequency = <40000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "U-Boot";
+				reg = <0x0 0x200000>;
+			};
+
+			partition@400000 {
+				label = "Filesystem";
+				reg = <0x200000 0xe00000>;
+			};
+		};
+	};
+};
+
+/* CON58 */
+&cp1_usb3_1 {
+	vbus-supply = <&cp1_reg_usb3_vbus0>;
+	current-limiter = <&cp1_reg_usb3_current_lim0>;
+	vbus-disable-delay = <500>;
+	status = "okay";
+};
+
+&cp1_utmi1 {
+	status = "okay";
+};