arm: dts: ls1028a: define QDS networking protocol combinations

Includes DT definition for the following serdes protocols using various
PHY cards: 85xx, 13xx, 65xx, 9999, 7777.

Note that the default device tree for QDS now uses 85xx.
Enabling any of the others requires patching the fsl-ls1028a-qds.dtsi
file (the includes at the bottom of the file).

The phy-handle is specified as a path rather than a label because it is
possible to use the #include multiple times (meaning that more than one
PHY riser card of one type is inserted), and therefore, there would be
duplicate labels with the same name.

LBRW means that the board needs lane B rework before using this dtsi.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

1 files changed, 28 insertions, 0 deletions

diff --git a/arch/arm/dts/fsl-sch-24801.dtsi b/arch/arm/dts/fsl-sch-24801.dtsi
new file mode 100644
index 00000000000..304afdabc59
--- /dev/null
+++ b/arch/arm/dts/fsl-sch-24801.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Device tree fragment for RCW SCH-24801 card
+ *
+ * Copyright 2019-2021 NXP Semiconductors
+ */
+
+/*
+ * SCH-24801 is a 4xSGMII add-on card used with various FSL QDS boards.
+ * It integrates a VSC8234 quad PHY which supports 4 SGMII interfaces.
+ * PHY addresses are 0x1c - 0x1f.
+ * On the card the first port is the top port (farthest from PEX connector).
+ */
+phy@1c {
+	reg = <0x1c>;
+};
+
+phy@1d {
+	reg = <0x1d>;
+};
+
+phy@1e {
+	reg = <0x1e>;
+};
+
+phy@1f {
+	reg = <0x1f>;
+};