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authorPatrick Delaunay2022-09-21 09:37:13 +0200
committerPatrice Chotard2022-09-23 14:35:45 +0200
commit9f7c58dc0deacd6c453ac628953741f1a6a68126 (patch)
tree893e659f70e6061811312a32a27536010fa65d1d /arch/arm/dts/stm32f746.dtsi
parent86d5a06ae3b826bf7b4627e926afd5378d88c574 (diff)
ARM: dts: stm32mp15: update DDR node
Remove the unnecessary nodes for TFABOOT and keep the mandatory part in SOC dtsi, only the DDRCTRL and DDRPHY addresses. This patch allows to manage the DDR configuration setting in U-Boot device tree only if it is needed, when CONFIG_SPL is defined. With TFABOOT, the DDR configuration is done in TF-A BL2 and the DDR size is dynamically computed in U-Boot since commit d72e7bbe7c28 ("ram: stm32mp1: compute DDR size from DDRCTL registers"). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Diffstat (limited to 'arch/arm/dts/stm32f746.dtsi')
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