diff options
author | Patrick Delaunay | 2020-03-06 17:54:41 +0100 |
---|---|---|
committer | Patrick Delaunay | 2020-03-24 14:18:36 +0100 |
commit | 1a4f57c895ccebc15a33a36f5c0fc0bcb1dbdea4 (patch) | |
tree | 429a4588e2da54d2ad5ebb0b0791c01e6f78f06f /arch/arm/dts/stm32mp15-u-boot.dtsi | |
parent | 0c90e0cf63531bfdfb09a54acbd28c53d4c261ea (diff) |
ARM: dts: stm32mp1: DT alignment with Linux 5.6-rc1
This commit manages diversity for STM32M15x SOCs with:
- dedicated files to support all STM32MP15 SOCs family.
The differences between those SOCs are:
-STM32MP151 [1]: common file.
-STM32MP153 [2]: STM32MP151 + CANs + a second CortexA7-CPU.
-STM32MP157 [3]: STM32MP153 + DSI + GPU.
- new files to manage security diversity on STM32MP15x SOCs.
On STM32MP15xY, "Y" gives information:
-Y = A means no cryp IP and no secure boot.
-Y = C means cryp IP + secure boot.
- stm32mp157 pinctrl files to better manage package diversity.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Diffstat (limited to 'arch/arm/dts/stm32mp15-u-boot.dtsi')
-rw-r--r-- | arch/arm/dts/stm32mp15-u-boot.dtsi | 155 |
1 files changed, 155 insertions, 0 deletions
diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi new file mode 100644 index 00000000000..8f9535a4dbc --- /dev/null +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright : STMicroelectronics 2018 + */ + +/ { + aliases { + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + gpio25 = &gpioz; + pinctrl0 = &pinctrl; + pinctrl1 = &pinctrl_z; + }; + + clocks { + u-boot,dm-pre-reloc; + }; + + /* need PSCI for sysreset during board_f */ + psci { + u-boot,dm-pre-proper; + }; + + reboot { + u-boot,dm-pre-reloc; + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&bsec { + u-boot,dm-pre-proper; +}; + +&clk_csi { + u-boot,dm-pre-reloc; +}; + +&clk_hsi { + u-boot,dm-pre-reloc; +}; + +&clk_hse { + u-boot,dm-pre-reloc; +}; + +&clk_lsi { + u-boot,dm-pre-reloc; +}; + +&clk_lse { + u-boot,dm-pre-reloc; +}; + +&gpioa { + u-boot,dm-pre-reloc; +}; + +&gpiob { + u-boot,dm-pre-reloc; +}; + +&gpioc { + u-boot,dm-pre-reloc; +}; + +&gpiod { + u-boot,dm-pre-reloc; +}; + +&gpioe { + u-boot,dm-pre-reloc; +}; + +&gpiof { + u-boot,dm-pre-reloc; +}; + +&gpiog { + u-boot,dm-pre-reloc; +}; + +&gpioh { + u-boot,dm-pre-reloc; +}; + +&gpioi { + u-boot,dm-pre-reloc; +}; + +&gpioj { + u-boot,dm-pre-reloc; +}; + +&gpiok { + u-boot,dm-pre-reloc; +}; + +&gpioz { + u-boot,dm-pre-reloc; +}; + +&iwdg2 { + u-boot,dm-pre-reloc; +}; + +/* pre-reloc probe = reserve video frame buffer in video_reserve() */ +<dc { + u-boot,dm-pre-proper; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&pinctrl_z { + u-boot,dm-pre-reloc; +}; + +&pwr_regulators { + u-boot,dm-pre-reloc; +}; + +&rcc { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <0>; +}; + +&sdmmc1 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; +}; + +&sdmmc2 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; +}; + +&sdmmc3 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; +}; + +&usbotg_hs { + compatible = "st,stm32mp1-hsotg", "snps,dwc2"; +}; |