diff options
| author | Patrick Delaunay | 2019-11-06 16:16:33 +0100 |
|---|---|---|
| committer | Patrick Delaunay | 2019-11-26 10:11:48 +0100 |
| commit | 62d620c243ead4e34de5ab8c0c2ea215f9972109 (patch) | |
| tree | 1e6ac5b37ccf585cc4be496404a86adee1c65025 /arch/arm/dts/stm32mp157c.dtsi | |
| parent | e07a86b5e320113c31221029179db29e392fc090 (diff) | |
ARM: dts: stm32: DT alignment with kernel v5.4-rc4
Device tree and binding alignment with kernel v5.4-rc4
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Diffstat (limited to 'arch/arm/dts/stm32mp157c.dtsi')
| -rw-r--r-- | arch/arm/dts/stm32mp157c.dtsi | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi index a6045dd682c..6c670cf9a36 100644 --- a/arch/arm/dts/stm32mp157c.dtsi +++ b/arch/arm/dts/stm32mp157c.dtsi @@ -109,6 +109,12 @@ }; }; + booster: regulator-booster { + compatible = "st,stm32mp1-booster"; + st,syscfg = <&syscfg>; + status = "disabled"; + }; + reboot { compatible = "syscon-reboot"; regmap = <&rcc>; @@ -140,6 +146,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -168,6 +175,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -194,6 +202,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -222,6 +231,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -279,6 +289,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -300,6 +311,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -321,6 +333,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -574,6 +587,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -604,6 +618,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -677,6 +692,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -701,6 +717,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; timer@15 { @@ -724,6 +741,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -990,6 +1008,7 @@ clocks = <&rcc ADC12>, <&rcc ADC12_K>; clock-names = "bus", "adc"; interrupt-controller; + st,syscfg = <&syscfg>; #interrupt-cells = <1>; #address-cells = <1>; #size-cells = <0>; @@ -1313,6 +1332,10 @@ <0x89010000 0x1000>, <0x89020000 0x1000>; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>, + <&mdma1 20 0x10 0x12000a08 0x0 0x0>, + <&mdma1 21 0x10 0x12000a0a 0x0 0x0>; + dma-names = "tx", "rx", "ecc"; clocks = <&rcc FMC_K>; resets = <&rcc FMC_R>; status = "disabled"; @@ -1323,6 +1346,9 @@ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; reg-names = "qspi", "qspi_mm"; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>, + <&mdma1 22 0x10 0x100008 0x0 0x0>; + dma-names = "tx", "rx"; clocks = <&rcc QSPI_K>; resets = <&rcc QSPI_R>; status = "disabled"; |