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authorJagan Teki2015-06-27 00:51:33 +0530
committerJagan Teki2015-07-01 21:15:03 +0530
commita8a8fc9ceea8430224c8c0ac932a75c029a1e225 (patch)
tree5d7b6796ddbd220e41599497974b55cd60f17aac /arch/arm/dts/zynq-7000.dtsi
parent9f7a45020bc30934ed4ba3f0c2e4535248934186 (diff)
dts: zynq: Add zynq spi controller nodes
This patch adds zynq spi controller nodes in zynq-7000.dtsi. Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
Diffstat (limited to 'arch/arm/dts/zynq-7000.dtsi')
-rw-r--r--arch/arm/dts/zynq-7000.dtsi24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 2d076f194e0..f66f8dcaf8d 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -109,6 +109,30 @@
interrupts = <0 50 4>;
};
+ spi0: spi@e0006000 {
+ compatible = "xlnx,zynq-spi";
+ reg = <0xe0006000 0x1000>;
+ status = "disabled";
+ interrupt-parent = <&intc>;
+ interrupts = <0 26 4>;
+ clocks = <&clkc 25>, <&clkc 34>;
+ clock-names = "ref_clk", "pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@e0007000 {
+ compatible = "xlnx,zynq-spi";
+ reg = <0xe0007000 0x1000>;
+ status = "disabled";
+ interrupt-parent = <&intc>;
+ interrupts = <0 49 4>;
+ clocks = <&clkc 26>, <&clkc 35>;
+ clock-names = "ref_clk", "pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
gem0: ethernet@e000b000 {
compatible = "cdns,gem";
reg = <0xe000b000 0x4000>;