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authorTom Rini2018-07-27 13:09:30 -0400
committerTom Rini2018-07-27 13:09:30 -0400
commit0e8a8a311020d317fcfcf594e8e3fb1598134593 (patch)
tree5410444f60514df7074ba038aa3e33c44f7dcf23 /arch/arm/dts
parent11e409284ee593c980e16d93d12c5e19c99b62c0 (diff)
parent86b840b78d0eba652f65841a870d232ab743612e (diff)
Merge git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'arch/arm/dts')
-rw-r--r--arch/arm/dts/fsl-ls1012a-2g5rdb.dts4
-rw-r--r--arch/arm/dts/fsl-ls1012a-qds.dtsi4
-rw-r--r--arch/arm/dts/fsl-ls1012a-rdb.dtsi4
-rw-r--r--arch/arm/dts/fsl-ls1012a.dtsi8
4 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/dts/fsl-ls1012a-2g5rdb.dts b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
index db23cf87ed7..cdd4ce45aaf 100644
--- a/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
+++ b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
@@ -40,3 +40,7 @@
&duart0 {
status = "okay";
};
+
+&sata {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi
index d069b603abd..661af0e49e6 100644
--- a/arch/arm/dts/fsl-ls1012a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi
@@ -125,3 +125,7 @@
status = "okay";
phy_type = "ulpi";
};
+
+&sata {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
index 201e5faead1..757e2eb3519 100644
--- a/arch/arm/dts/fsl-ls1012a-rdb.dtsi
+++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
@@ -34,3 +34,7 @@
&duart0 {
status = "okay";
};
+
+&sata {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index be990765506..f22cbf4b2a2 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -134,6 +134,14 @@
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
+ sata: sata@3200000 {
+ compatible = "fsl,ls1012a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>;
+ interrupts = <0 69 4>;
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
usb0: usb2@8600000 {
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
reg = <0x0 0x8600000 0x0 0x1000>;