Merge git://git.denx.de/u-boot-imx

29 files changed, 723 insertions, 57 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7bec3d6cfea..b3a240590f4 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -400,24 +400,33 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
 
 dtb-$(CONFIG_MX53) += imx53-cx9020.dtb
 
-dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
-	imx6sl-evk.dtb \
-	imx6sll-evk.dtb \
+dtb-$(CONFIG_MX6QDL) += \
 	imx6dl-icore.dtb \
 	imx6dl-icore-mipi.dtb \
 	imx6dl-icore-rqs.dtb \
+	imx6dl-mamoj.dtb \
 	imx6q-cm-fx6.dtb \
 	imx6q-icore.dtb \
 	imx6q-icore-mipi.dtb \
 	imx6q-icore-rqs.dtb \
-	imx6q-logicpd.dtb \
+	imx6q-logicpd.dtb
+
+dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb
+
+dtb-$(CONFIG_MX6SL) += imx6sll-evk.dtb
+
+dtb-$(CONFIG_MX6SX) += \
 	imx6sx-sabreauto.dtb \
-	imx6sx-sdb.dtb \
+	imx6sx-sdb.dtb
+
+dtb-$(CONFIG_MX6UL) += \
 	imx6ul-geam-kit.dtb \
 	imx6ul-isiot-emmc.dtb \
 	imx6ul-isiot-nand.dtb \
 	imx6ul-opos6uldev.dtb
 
+dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb
+
 dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
 	imx7d-sdb.dtb
 
diff --git a/arch/arm/dts/imx53-kp.dts b/arch/arm/dts/imx53-kp.dts
new file mode 100644
index 00000000000..fd64a9f2f6d
--- /dev/null
+++ b/arch/arm/dts/imx53-kp.dts
@@ -0,0 +1,135 @@
+/*
+ * Copyright 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier:     GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "imx53.dtsi"
+#include "imx53-pinfunc.h"
+
+/ {
+	model = "K+P iMX53";
+	compatible = "kp,imx53-kp", "fsl,imx53";
+
+	chosen {
+		stdout-path = &uart2;
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eth>;
+	phy-mode = "rmii";
+	phy-reset-gpios = <&gpio7 6 0>;
+	status = "okay";
+};
+
+&i2c2 {
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	clock_frequency = <100000>;
+
+	scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+
+	status = "okay";
+
+	pmic: mc34708@8 {
+		compatible = "fsl,mc34708";
+		reg = <0x8>;
+	};
+};
+
+&i2c3 {
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	clock_frequency = <100000>;
+
+	scl-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	imx53-kp {
+		pinctrl_eth: ethgrp {
+			fsl,pins = <
+				MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
+				MX53_PAD_FEC_MDC__FEC_MDC 0x4
+				MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
+				MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
+				MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
+				MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
+				MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
+				MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
+				/* The RX_ER pin needs to be pull down */
+				/* for this device */
+				MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1c0
+				MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
+				>;
+		};
+
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				/* PHY RESET */
+				MX53_PAD_PATA_DA_0__GPIO7_6 0x182
+				/* VBUS_PWR_EN */
+				MX53_PAD_PATA_DA_2__GPIO7_8 0x1e4
+				/* BOOSTER_OFF */
+				MX53_PAD_EIM_CS0__GPIO2_23 0x1e4
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX53_PAD_KEY_ROW3__I2C2_SDA
+						 (0x1ee | IMX_PAD_SION)
+				MX53_PAD_KEY_COL3__I2C2_SCL
+						 (0x1ee | IMX_PAD_SION)
+			>;
+		};
+
+		pinctrl_i2c2_gpio: i2c2grpgpio {
+			fsl,pins = <
+				MX53_PAD_KEY_ROW3__GPIO4_13 0x1e4
+				MX53_PAD_KEY_COL3__GPIO4_12 0x1e4
+			>;
+		};
+
+		pinctrl_i2c3: i2c3grp {
+			fsl,pins = <
+				MX53_PAD_GPIO_6__I2C3_SDA (0x1ee | IMX_PAD_SION)
+				MX53_PAD_GPIO_5__I2C3_SCL (0x1ee | IMX_PAD_SION)
+			>;
+		};
+
+		pinctrl_i2c3_gpio: i2c3grpgpio {
+			fsl,pins = <
+				MX53_PAD_GPIO_6__GPIO1_6 0x1e4
+				MX53_PAD_GPIO_5__GPIO1_5 0x1e4
+			>;
+		};
+
+		pinctrl_uart2: uart2grp {
+			fsl,pins = <
+				MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
+				MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
+			>;
+		};
+	};
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx53-pinfunc.h b/arch/arm/dts/imx53-pinfunc.h
index aec406bc65e..baf710d0df2 100644
--- a/arch/arm/dts/imx53-pinfunc.h
+++ b/arch/arm/dts/imx53-pinfunc.h
@@ -10,6 +10,7 @@
 #ifndef __DTS_IMX53_PINFUNC_H
 #define __DTS_IMX53_PINFUNC_H
 
+#define IMX_PAD_SION       0x40000000
 /*
  * The pin function ID is a tuple of
  * <mux_reg conf_reg input_reg mux_mode input_val>
diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi
index f68e88585e4..64591f9d476 100644
--- a/arch/arm/dts/imx53.dtsi
+++ b/arch/arm/dts/imx53.dtsi
@@ -21,6 +21,16 @@
 / {
 	aliases {
 		serial1 = &uart2;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		gpio5 = &gpio6;
+		gpio6 = &gpio7;
+		i2c0 = &i2c1;
+		i2c1 = &i2c2;
+		i2c2 = &i2c3;
 	};
 
 	tzic: tz-interrupt-controller@fffc000 {
@@ -73,6 +83,66 @@
 				#clock-cells = <1>;
 			};
 
+			gpio1: gpio@53f84000 {
+				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+				reg = <0x53f84000 0x4000>;
+				interrupts = <50 51>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio2: gpio@53f88000 {
+				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+				reg = <0x53f88000 0x4000>;
+				interrupts = <52 53>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio3: gpio@53f8c000 {
+				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+				reg = <0x53f8c000 0x4000>;
+				interrupts = <54 55>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio4: gpio@53f90000 {
+				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+				reg = <0x53f90000 0x4000>;
+				interrupts = <56 57>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio5: gpio@53fdc000 {
+				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+				reg = <0x53fdc000 0x4000>;
+				interrupts = <103 104>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio6: gpio@53fe0000 {
+				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+				reg = <0x53fe0000 0x4000>;
+				interrupts = <105 106>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
 			gpio7: gpio@53fe4000 {
 				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 				reg = <0x53fe4000 0x4000>;
@@ -82,6 +152,16 @@
 				interrupt-controller;
 				#interrupt-cells = <2>;
 			};
+
+			i2c3: i2c@53fec000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
+				reg = <0x53fec000 0x4000>;
+				interrupts = <64>;
+				clocks = <&clks IMX5_CLK_I2C3_GATE>;
+				status = "disabled";
+			};
 		};
 
 		aips@60000000 {	/* AIPS2 */
@@ -102,7 +182,6 @@
 				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
 			};
 
-
 			fec: ethernet@63fec000 {
 				compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 				reg = <0x63fec000 0x4000>;
@@ -113,6 +192,26 @@
 				clock-names = "ipg", "ahb", "ptp";
 				status = "disabled";
 			};
+
+			i2c2: i2c@63fc4000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
+				reg = <0x63fc4000 0x4000>;
+				interrupts = <63>;
+				clocks = <&clks IMX5_CLK_I2C2_GATE>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@63fc8000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
+				reg = <0x63fc8000 0x4000>;
+				interrupts = <62>;
+				clocks = <&clks IMX5_CLK_I2C1_GATE>;
+				status = "disabled";
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/imx6dl-icore-mipi-u-boot.dtsi b/arch/arm/dts/imx6dl-icore-mipi-u-boot.dtsi
new file mode 100644
index 00000000000..86e8da761d1
--- /dev/null
+++ b/arch/arm/dts/imx6dl-icore-mipi-u-boot.dtsi
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6qdl-icore-u-boot.dtsi"
+
+&usdhc3 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx6dl-icore-mipi.dts b/arch/arm/dts/imx6dl-icore-mipi.dts
index 3a444c0d986..39bdf2d55b3 100644
--- a/arch/arm/dts/imx6dl-icore-mipi.dts
+++ b/arch/arm/dts/imx6dl-icore-mipi.dts
@@ -16,6 +16,5 @@
 };
 
 &usdhc3 {
-	u-boot,dm-spl;
 	status = "okay";
 };
diff --git a/arch/arm/dts/imx6dl-icore-rqs-u-boot.dtsi b/arch/arm/dts/imx6dl-icore-rqs-u-boot.dtsi
new file mode 100644
index 00000000000..210b9302643
--- /dev/null
+++ b/arch/arm/dts/imx6dl-icore-rqs-u-boot.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6qdl-icore-rqs-u-boot.dtsi"
diff --git a/arch/arm/dts/imx6dl-icore-u-boot.dtsi b/arch/arm/dts/imx6dl-icore-u-boot.dtsi
new file mode 100644
index 00000000000..5bd3df96f51
--- /dev/null
+++ b/arch/arm/dts/imx6dl-icore-u-boot.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6qdl-icore-u-boot.dtsi"
diff --git a/arch/arm/dts/imx6dl-mamoj-u-boot.dtsi b/arch/arm/dts/imx6dl-mamoj-u-boot.dtsi
new file mode 100644
index 00000000000..d4c3c0bdf0f
--- /dev/null
+++ b/arch/arm/dts/imx6dl-mamoj-u-boot.dtsi
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6qdl-u-boot.dtsi"
+
+&usdhc3 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx6dl-mamoj.dts b/arch/arm/dts/imx6dl-mamoj.dts
new file mode 100644
index 00000000000..3f6d8aa4a25
--- /dev/null
+++ b/arch/arm/dts/imx6dl-mamoj.dts
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 BTicino
+ * Copyright (C) 2018 Amarula Solutions B.V.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6dl.dtsi"
+
+/ {
+	model = "BTicino i.MX6DL Mamoj board";
+	compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl";
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "mii";
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	status = "okay";
+
+	pmic: pfuze100@08 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			/* CPU vdd_arm core */
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			/* SOC vdd_soc */
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			/* I/O power GEN_3V3 */
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* DDR memory */
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* DDR memory */
+			sw3b_reg: sw3b {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* not used */
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			/* not used */
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			/* PMIC vsnvs. EX boot mode */
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* not used */
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			/* not used */
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			/* not used */
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			/* 1v8 general power */
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			/* 2v8 general power IMX6 */
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			/* 3v3 Ethernet */
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	bus-width = <8>;
+	non-removable;
+	keep-power-in-suspend;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b1
+			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x1b0b0
+			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x1b0b0
+			MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2	0x1b0b0
+			MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3	0x1b0b0
+			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
+			MX6QDL_PAD_GPIO_19__ENET_TX_ER		0x1b0b0
+			MX6QDL_PAD_GPIO_18__ENET_RX_CLK		0x1b0b1
+			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0
+			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0
+			MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2	0x1b0b0
+			MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3      0x1b0b0
+			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0
+			MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x1b0b0
+			MX6QDL_PAD_KEY_COL3__ENET_CRS		0x1b0b0
+			MX6QDL_PAD_KEY_ROW1__ENET_COL		0x1b0b0
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_3__I2C3_SCL     0x4001b8b1
+			MX6QDL_PAD_GPIO_6__I2C3_SDA     0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_7__I2C4_SCL	0x4001b8b1
+			MX6QDL_PAD_GPIO_8__I2C4_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
+			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD	0x17059
+			MX6QDL_PAD_SD3_CLK__SD3_CLK	0x10059
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0	0x17059
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1	0x17059
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2	0x17059
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3	0x17059
+			MX6QDL_PAD_SD3_DAT4__SD3_DATA4	0x17059
+			MX6QDL_PAD_SD3_DAT5__SD3_DATA5	0x17059
+			MX6QDL_PAD_SD3_DAT6__SD3_DATA6	0x17059
+			MX6QDL_PAD_SD3_DAT7__SD3_DATA7	0x17059
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx6q-icore-mipi-u-boot.dtsi b/arch/arm/dts/imx6q-icore-mipi-u-boot.dtsi
new file mode 100644
index 00000000000..86e8da761d1
--- /dev/null
+++ b/arch/arm/dts/imx6q-icore-mipi-u-boot.dtsi
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6qdl-icore-u-boot.dtsi"
+
+&usdhc3 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx6q-icore-mipi.dts b/arch/arm/dts/imx6q-icore-mipi.dts
index 527f52c8866..e7c5616a631 100644
--- a/arch/arm/dts/imx6q-icore-mipi.dts
+++ b/arch/arm/dts/imx6q-icore-mipi.dts
@@ -16,6 +16,5 @@
 };
 
 &usdhc3 {
-	u-boot,dm-spl;
 	status = "okay";
 };
diff --git a/arch/arm/dts/imx6q-icore-rqs-u-boot.dtsi b/arch/arm/dts/imx6q-icore-rqs-u-boot.dtsi
new file mode 100644
index 00000000000..210b9302643
--- /dev/null
+++ b/arch/arm/dts/imx6q-icore-rqs-u-boot.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6qdl-icore-rqs-u-boot.dtsi"
diff --git a/arch/arm/dts/imx6q-icore-u-boot.dtsi b/arch/arm/dts/imx6q-icore-u-boot.dtsi
new file mode 100644
index 00000000000..5bd3df96f51
--- /dev/null
+++ b/arch/arm/dts/imx6q-icore-u-boot.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6qdl-icore-u-boot.dtsi"
diff --git a/arch/arm/dts/imx6qdl-icore-rqs-u-boot.dtsi b/arch/arm/dts/imx6qdl-icore-rqs-u-boot.dtsi
new file mode 100644
index 00000000000..458debfbabd
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-icore-rqs-u-boot.dtsi
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6qdl-u-boot.dtsi"
+
+&usdhc3 {
+	u-boot,dm-spl;
+};
+
+&usdhc4 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc4 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/dts/imx6qdl-icore-rqs.dtsi
index 4f7f10203d3..d797a034f76 100644
--- a/arch/arm/dts/imx6qdl-icore-rqs.dtsi
+++ b/arch/arm/dts/imx6qdl-icore-rqs.dtsi
@@ -105,7 +105,6 @@
 };
 
 &usdhc3 {
-	u-boot,dm-spl;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc3>;
 	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
@@ -114,7 +113,6 @@
 };
 
 &usdhc4 {
-	u-boot,dm-spl;
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc4>;
 	pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
@@ -176,7 +174,6 @@
 	};
 
 	pinctrl_usdhc3: usdhc3grp {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17070
 			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10070
@@ -188,7 +185,6 @@
 	};
 
 	pinctrl_usdhc4: usdhc4grp {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17070
 			MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10070
diff --git a/arch/arm/dts/imx6qdl-icore-u-boot.dtsi b/arch/arm/dts/imx6qdl-icore-u-boot.dtsi
new file mode 100644
index 00000000000..d45c20b10ca
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-icore-u-boot.dtsi
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6qdl-u-boot.dtsi"
+
+&usdhc1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx6qdl-icore.dtsi b/arch/arm/dts/imx6qdl-icore.dtsi
index 913dc99c54f..5eccda800da 100644
--- a/arch/arm/dts/imx6qdl-icore.dtsi
+++ b/arch/arm/dts/imx6qdl-icore.dtsi
@@ -122,7 +122,6 @@
 };
 
 &usdhc1 {
-	u-boot,dm-spl;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc1>;
 	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
@@ -221,7 +220,6 @@
 	};
 
 	pinctrl_usdhc1: usdhc1grp {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17070
 			MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10070
@@ -233,7 +231,6 @@
 	};
 
 	pinctrl_usdhc3: usdhc3grp {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
 			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
diff --git a/arch/arm/dts/imx6qdl-u-boot.dtsi b/arch/arm/dts/imx6qdl-u-boot.dtsi
new file mode 100644
index 00000000000..e6363aa1c1a
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-u-boot.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/ {
+	soc {
+		u-boot,dm-spl;
+
+		aips-bus@02000000 {
+			u-boot,dm-spl;
+		};
+
+		aips-bus@02100000 {
+			u-boot,dm-spl;
+		};
+	};
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
index e04b57089a6..b13b0b2db88 100644
--- a/arch/arm/dts/imx6qdl.dtsi
+++ b/arch/arm/dts/imx6qdl.dtsi
@@ -77,7 +77,6 @@
 		compatible = "simple-bus";
 		interrupt-parent = <&gpc>;
 		ranges;
-		u-boot,dm-spl;
 
 		dma_apbh: dma-apbh@00110000 {
 			compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
@@ -226,7 +225,6 @@
 			#size-cells = <1>;
 			reg = <0x02000000 0x100000>;
 			ranges;
-			u-boot,dm-spl;
 
 			spba-bus@02000000 {
 				compatible = "fsl,spba-bus", "simple-bus";
@@ -518,7 +516,6 @@
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
-				u-boot,dm-spl;
 			};
 
 			gpio2: gpio@020a0000 {
@@ -808,7 +805,6 @@
 			iomuxc: iomuxc@020e0000 {
 				compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 				reg = <0x020e0000 0x4000>;
-				u-boot,dm-spl;
 			};
 
 			ldb: ldb@020e0008 {
@@ -893,7 +889,6 @@
 			#size-cells = <1>;
 			reg = <0x02100000 0x100000>;
 			ranges;
-			u-boot,dm-spl;
 
 			crypto: caam@2100000 {
 				compatible = "fsl,sec-v4.0";
diff --git a/arch/arm/dts/imx6ul-geam-kit-u-boot.dtsi b/arch/arm/dts/imx6ul-geam-kit-u-boot.dtsi
new file mode 100644
index 00000000000..d1b77ba2951
--- /dev/null
+++ b/arch/arm/dts/imx6ul-geam-kit-u-boot.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6ul-u-boot.dtsi"
+
+&usdhc1 {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	pinctrl_usdhc1: usdhc1grp {
+		u-boot,dm-spl;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+		u-boot,dm-spl;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+		u-boot,dm-spl;
+	};
+};
diff --git a/arch/arm/dts/imx6ul-geam-kit.dts b/arch/arm/dts/imx6ul-geam-kit.dts
index 15e3f941538..07c21cb0a2d 100644
--- a/arch/arm/dts/imx6ul-geam-kit.dts
+++ b/arch/arm/dts/imx6ul-geam-kit.dts
@@ -87,7 +87,6 @@
 };
 
 &usdhc1 {
-	u-boot,dm-spl;
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc1>;
 	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
@@ -135,7 +134,6 @@
 	};
 
 	pinctrl_usdhc1: usdhc1grp {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
 			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
@@ -147,7 +145,6 @@
 	};
 
 	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
 			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
@@ -159,7 +156,6 @@
 	};
 
 	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
 			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
diff --git a/arch/arm/dts/imx6ul-isiot-emmc-u-boot.dtsi b/arch/arm/dts/imx6ul-isiot-emmc-u-boot.dtsi
new file mode 100644
index 00000000000..7d0cc154cf2
--- /dev/null
+++ b/arch/arm/dts/imx6ul-isiot-emmc-u-boot.dtsi
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6ul-isiot-u-boot.dtsi"
+
+&usdhc2 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx6ul-isiot-emmc.dts b/arch/arm/dts/imx6ul-isiot-emmc.dts
index a611e3bba55..50ce2d798e6 100644
--- a/arch/arm/dts/imx6ul-isiot-emmc.dts
+++ b/arch/arm/dts/imx6ul-isiot-emmc.dts
@@ -42,6 +42,7 @@
 
 /dts-v1/;
 
+#include "imx6ul.dtsi"
 #include "imx6ul-isiot.dtsi"
 
 / {
@@ -51,29 +52,5 @@
 
 &usdhc2 {
 	u-boot,dm-spl;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc2>;
-	cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
-	bus-width = <8>;
-	no-1-8-v;
 	status = "okay";
 };
-
-&iomuxc {
-	pinctrl_usdhc2: usdhc2grp {
-		u-boot,dm-spl;
-		fsl,pins = <
-			MX6UL_PAD_NAND_RE_B__USDHC2_CLK      0x17070
-			MX6UL_PAD_NAND_WE_B__USDHC2_CMD      0x10070
-			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0  0x17070
-			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1  0x17070
-			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2  0x17070
-			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3  0x17070
-			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4  0x17070
-			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5  0x17070
-			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6  0x17070
-			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7  0x17070
-			MX6UL_PAD_NAND_ALE__USDHC2_RESET_B   0x17070
-		>;
-	};
-};
diff --git a/arch/arm/dts/imx6ul-isiot-nand.dts b/arch/arm/dts/imx6ul-isiot-nand.dts
index 12a35284285..ffdaf34efb4 100644
--- a/arch/arm/dts/imx6ul-isiot-nand.dts
+++ b/arch/arm/dts/imx6ul-isiot-nand.dts
@@ -42,6 +42,7 @@
 
 /dts-v1/;
 
+#include "imx6ul.dtsi"
 #include "imx6ul-isiot.dtsi"
 
 / {
diff --git a/arch/arm/dts/imx6ul-isiot-u-boot.dtsi b/arch/arm/dts/imx6ul-isiot-u-boot.dtsi
new file mode 100644
index 00000000000..f98c3957472
--- /dev/null
+++ b/arch/arm/dts/imx6ul-isiot-u-boot.dtsi
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6ul-u-boot.dtsi"
+
+&usdhc1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx6ul-isiot.dtsi b/arch/arm/dts/imx6ul-isiot.dtsi
index 5007a88f45e..4ed7313683d 100644
--- a/arch/arm/dts/imx6ul-isiot.dtsi
+++ b/arch/arm/dts/imx6ul-isiot.dtsi
@@ -42,7 +42,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include "imx6ul.dtsi"
 
 / {
 	memory {
@@ -82,7 +81,6 @@
 };
 
 &usdhc1 {
-	u-boot,dm-spl;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc1>;
 	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
@@ -91,6 +89,15 @@
 	status = "okay";
 };
 
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
+	bus-width = <8>;
+	no-1-8-v;
+	status = "disabled";
+};
+
 &iomuxc {
 	pinctrl_enet1: enet1grp {
 		fsl,pins = <
@@ -129,7 +136,6 @@
 	};
 
 	pinctrl_usdhc1: usdhc1grp {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
 			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
@@ -139,4 +145,21 @@
 			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
 		>;
 	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		u-boot,dm-spl;
+		fsl,pins = <
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK      0x17070
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD      0x10070
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0  0x17070
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1  0x17070
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2  0x17070
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3  0x17070
+			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4  0x17070
+			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5  0x17070
+			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6  0x17070
+			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7  0x17070
+			MX6UL_PAD_NAND_ALE__USDHC2_RESET_B   0x17070
+		>;
+	};
 };
diff --git a/arch/arm/dts/imx6ul-u-boot.dtsi b/arch/arm/dts/imx6ul-u-boot.dtsi
new file mode 100644
index 00000000000..08d7747e1c3
--- /dev/null
+++ b/arch/arm/dts/imx6ul-u-boot.dtsi
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/ {
+	soc {
+		u-boot,dm-spl;
+	};
+};
+
+&aips1 {
+	u-boot,dm-spl;
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&aips2 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi
index d5ce3f13c24..b33e6249774 100644
--- a/arch/arm/dts/imx6ul.dtsi
+++ b/arch/arm/dts/imx6ul.dtsi
@@ -134,7 +134,6 @@
 		compatible = "simple-bus";
 		interrupt-parent = <&gpc>;
 		ranges;
-		u-boot,dm-spl;
 
 		pmu {
 			compatible = "arm,cortex-a7-pmu";
@@ -186,7 +185,6 @@
 			#size-cells = <1>;
 			reg = <0x02000000 0x100000>;
 			ranges;
-			u-boot,dm-spl;
 
 			spba-bus@02000000 {
 				compatible = "fsl,spba-bus", "simple-bus";
@@ -418,7 +416,6 @@
 				#interrupt-cells = <2>;
 				gpio-ranges = <&iomuxc  0 23 10>, <&iomuxc 10 17 6>,
 					      <&iomuxc 16 33 16>;
-				u-boot,dm-spl;
 			};
 
 			gpio2: gpio@020a0000 {
@@ -455,7 +452,6 @@
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
-				u-boot,dm-spl;
 			};
 
 			gpio5: gpio@020ac000 {
@@ -654,7 +650,6 @@
 			iomuxc: iomuxc@020e0000 {
 				compatible = "fsl,imx6ul-iomuxc";
 				reg = <0x020e0000 0x4000>;
-				u-boot,dm-spl;
 			};
 
 			gpr: iomuxc-gpr@020e4000 {
@@ -735,7 +730,6 @@
 			#size-cells = <1>;
 			reg = <0x02100000 0x100000>;
 			ranges;
-			u-boot,dm-spl;
 
 			usbotg1: usb@02184000 {
 				compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";