diff options
author | Lokesh Vutla | 2013-12-10 15:02:22 +0530 |
---|---|---|
committer | Tom Rini | 2013-12-18 21:14:44 -0500 |
commit | d3daba10f159cca7e9d24c6f154926a9b92c75e3 (patch) | |
tree | 34dee6df0d4914e66bc0bc9a3c652b20fc0e7eb7 /arch/arm/include/asm/arch-am33xx/ddr_defs.h | |
parent | 965de8b91bddd1f5967240d1d44005719b09dd5e (diff) |
ARM: AM43xx: EPOS_EVM: Add support for LPDDR2
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
Adding LPDDR2 init sequence and register details for the same.
Below is the brief description of LPDDR2 init sequence:
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
-> Wait till initialization is complete and the configure MR registers.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-am33xx/ddr_defs.h')
-rw-r--r-- | arch/arm/include/asm/arch-am33xx/ddr_defs.h | 33 |
1 files changed, 31 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 2278358ab20..6af4b84e568 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -18,7 +18,11 @@ #define VTP_CTRL_READY (0x1 << 5) #define VTP_CTRL_ENABLE (0x1 << 6) #define VTP_CTRL_START_EN (0x1) +#ifdef CONFIG_AM43XX +#define DDR_CKE_CTRL_NORMAL 0x3 +#else #define DDR_CKE_CTRL_NORMAL 0x1 +#endif #define PHY_EN_DYN_PWRDN (0x1 << 20) /* Micron MT47H128M16RT-25E */ @@ -124,6 +128,14 @@ #define K4B2G1646EBIH9_PHY_WR_DATA 0x76 #define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B +#define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294 +#define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 +#define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 +#define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294 + /** * Configure DMM */ @@ -133,6 +145,7 @@ void config_dmm(const struct dmm_lisa_map_regs *regs); * Configure SDRAM */ void config_sdram(const struct emif_regs *regs, int nr); +void config_sdram_emif4d5(const struct emif_regs *regs, int nr); /** * Set SDRAM timings @@ -278,12 +291,27 @@ struct ddr_cmdtctrl { unsigned int resv2[12]; unsigned int dt0ioctl; unsigned int dt1ioctl; + unsigned int dt2ioctrl; + unsigned int dt3ioctrl; + unsigned int resv3[4]; + unsigned int emif_sdram_config_ext; +}; + +struct ctrl_ioregs { + unsigned int cm0ioctl; + unsigned int cm1ioctl; + unsigned int cm2ioctl; + unsigned int dt0ioctl; + unsigned int dt1ioctl; + unsigned int dt2ioctrl; + unsigned int dt3ioctrl; + unsigned int emif_sdram_config_ext; }; /** * Configure DDR io control registers */ -void config_io_ctrl(unsigned long val); +void config_io_ctrl(const struct ctrl_ioregs *ioregs); struct ddr_ctrl { unsigned int ddrioctrl; @@ -291,8 +319,9 @@ struct ddr_ctrl { unsigned int ddrckectrl; }; -void config_ddr(unsigned int pll, unsigned int ioctrl, +void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, int nr); +void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size); #endif /* _DDR_DEFS_H */ |