diff options
| author | Tom Rini | 2022-11-16 13:10:33 -0500 |
|---|---|---|
| committer | Tom Rini | 2022-12-05 16:06:07 -0500 |
| commit | ecc8d425fd50d894dd0a06796c17030ef4a7942f (patch) | |
| tree | 6fade563d93ccb2dc3c774bdcc3d2f5cf5b6403c /arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | |
| parent | 789bb9537a4427798e3e28ff0c6be2c27454315f (diff) | |
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and
CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many
cases they likely should come from the device tree instead. Move these
out of CONFIG namespace and in to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 85ac5eb2813..64dc7c88b7f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -33,8 +33,8 @@ #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) @@ -90,9 +90,9 @@ #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) #define QMAN_CQSIDR_REG 0x20a80 -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL +#define CFG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL +#define CFG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL +#define CFG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL /* LUT registers */ #ifdef CONFIG_ARCH_LS1012A #define PCIE_LUT_BASE 0xC0000 |