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authorRamneek Mehresh2015-05-29 14:47:20 +0530
committerMarek Vasut2015-07-22 08:55:45 +0200
commitd09e401b439859cf9435bfe363265b4322e93cd9 (patch)
tree276eee65e3f954823e777a6f5503ddff38051463 /arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
parentba92ee06a5b792e5cbc144f95883cc54f4982255 (diff)
arch: arm: fsl: Add XHCI support for LS1021A
Add base register address information for USB XHCI controller on LS1021A Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h')
-rw-r--r--arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 6a330cc2aff..e759b52d606 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -396,4 +396,14 @@ struct ccsr_cci400 {
} pcounter[4]; /* Performance Counter */
u8 res_e004[0x10000 - 0xe004];
};
+
+/* USB-XHCI */
+#define FSL_XHCI_BASE 0x3100000
+#define FSL_OCP1_SCP_BASE 0x4a084c00
+#define FSL_OTG_WRAPPER_BASE 0x4A020000
+
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
+ CONFIG_SYS_FSL_XHCI_USB2_ADDR}
#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */