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authorPeng Fan2015-08-17 16:11:01 +0800
committerStefano Babic2015-09-02 15:34:12 +0200
commit775d591f5d6e9266642c89d731b22263fc07e1c6 (patch)
tree2a875c3e4c1ae5b70bbdd4944326727fb9bb433d /arch/arm/include/asm/arch-mx6
parent1b811e285c257a9f9545b9f0efad423541bb89e1 (diff)
imx: mx6: ddr add mpzqlp2ctl entry
Add mpzqlp2ctl entry for mx6_mmdc_calibration. MMDC_MPZQLP2CTL register is for init tZQINIT, tZQCL, tZQCS for LPDDR2 chips. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
Diffstat (limited to 'arch/arm/include/asm/arch-mx6')
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6-ddr.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 235a44a554f..b7bae7b17f9 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -414,6 +414,8 @@ struct mx6_mmdc_calibration {
/* write delay */
u32 p0_mpwrdlctl;
u32 p1_mpwrdlctl;
+ /* lpddr2 zq hw calibration */
+ u32 mpzqlp2ctl;
};
/* configure iomux (pinctl/padctl) */