diff options
| author | Svyatoslav Ryhel | 2023-07-03 18:11:58 +0300 |
|---|---|---|
| committer | Svyatoslav Ryhel | 2023-12-19 21:24:11 +0200 |
| commit | e63ab85dba80f15f6740821a4669569564537f94 (patch) | |
| tree | 079f3d6242b77b5fd0de7f429e559a0a5c55de61 /arch/arm/include/asm/arch-tegra30 | |
| parent | 1ba80d1b2ce474e0e924bc9c0c1b44d3554204b1 (diff) | |
ARM: tegra30: clock: implement PLLD2 support
PLLD2 is a simple clock (controlled by 2 registers) and appears starting
from T30. Primary use of PLLD2 is as main HDMI clock parent.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra30')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra30/clock-tables.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-tegra30/clock-tables.h b/arch/arm/include/asm/arch-tegra30/clock-tables.h index 6c899ff64c8..5ebcbc2c9ad 100644 --- a/arch/arm/include/asm/arch-tegra30/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra30/clock-tables.h @@ -23,6 +23,7 @@ enum clock_id { CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, CLOCK_ID_EPCI, CLOCK_ID_SFROM32KHZ, + CLOCK_ID_DISPLAY2, /* These are the base clocks (inputs to the Tegra SOC) */ CLOCK_ID_32KHZ, @@ -30,7 +31,6 @@ enum clock_id { CLOCK_ID_CLK_M, CLOCK_ID_COUNT, /* number of PLLs */ - CLOCK_ID_DISPLAY2, /* Tegra3, placeholder */ CLOCK_ID_NONE = -1, }; |