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authorJesse Taube2022-02-11 19:32:34 -0500
committerAndre Przywara2022-03-03 01:24:06 +0000
commit0dcdaff8b88e996de5d9c91141084cbfcfb01be6 (patch)
treebf7cb0658f5ec1fb716ae9e12190ca58155a5017 /arch/arm/include/asm
parenta08b04b5c75a7e9122dfc733c66b978aa0afe4ba (diff)
mach-sunxi: Add SPL SPI boot for SUNIV
The SUNIV SoCs come with a sun6i-style SPI controller at the base address of sun4i SPI controller. The module clock of the SPI controller is missing which leaves us running directly from the AHB clock, which is set to 200MHz. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> [Icenowy: Original implementation] Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> [Jesse: adaptation to Upstream U-Boot] Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r--arch/arm/include/asm/arch-sunxi/gpio.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 7f7eb0517cf..edd0fbf49fe 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -160,6 +160,7 @@ enum sunxi_gpio_number {
#define SUNXI_GPC_SDC2 3
#define SUN6I_GPC_SDC3 4
#define SUN50I_GPC_SPI0 4
+#define SUNIV_GPC_SPI0 2
#define SUNXI_GPD_LCD0 2
#define SUNXI_GPD_LVDS0 3