diff options
| author | York Sun | 2018-11-05 18:02:09 +0000 |
|---|---|---|
| committer | York Sun | 2018-12-06 14:37:19 -0800 |
| commit | 56db948b85aa7c03c79b2c796500de4523924a9d (patch) | |
| tree | 66a4244e1f6382be7584687574284be3b92cb71b /arch/arm/include | |
| parent | 5a73ec6169d1db85eacc4ad2fc74dad92a846c9e (diff) | |
armv8: fsl-layerscape: Update parsing boot source
Workaround of erratum A010539 clears the RCW source field in PORSR1
register, causing failure of detecting boot source using this method.
Use SMC call if U-Boot runs at EL2. If SMC is not implemented or
running at EL3, continue to read PORSR1 and presume QSPI as boot
source if erratum workaround A010539 is enabled and RCW source is
cleared.
Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index ef228b64437..daa1c70b3a1 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -56,6 +56,7 @@ struct cpu_type { #ifdef CONFIG_TFABOOT #define SMC_DRAM_BANK_INFO (0xC200FF12) +#define SIP_SVC_RCW 0xC200FF18 phys_size_t tfa_get_dram_size(void); |