diff options
| author | Bryan Brinsko | 2015-03-24 11:25:12 -0500 |
|---|---|---|
| committer | Albert ARIBAUD | 2015-04-16 14:59:33 +0200 |
| commit | 97840b5d1fe0960134c3553a9d9d1c1cd1be784d (patch) | |
| tree | 3ae40c9ca7eceb5306544d318e38e6dad6dcedb2 /arch/arm/lib | |
| parent | 9ba379ade789e41cc4132d622315f3f021a47b9b (diff) | |
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching
The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being
properly set to allow for the configuration specified caching modes to
be active over DRAM. This commit fixes those issues.
Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com>
Diffstat (limited to 'arch/arm/lib')
| -rw-r--r-- | arch/arm/lib/cache-cp15.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 0291afa7bd5..c65e068857a 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -96,9 +96,23 @@ static inline void mmu_setup(void) dram_bank_mmu_setup(i); } +#ifdef CONFIG_ARMV7 + /* Set TTBR0 */ + reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK; +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) + reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT; +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) + reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA; +#else + reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB; +#endif + asm volatile("mcr p15, 0, %0, c2, c0, 0" + : : "r" (reg) : "memory"); +#else /* Copy the page table address to cp15 */ asm volatile("mcr p15, 0, %0, c2, c0, 0" : : "r" (gd->arch.tlb_addr) : "memory"); +#endif /* Set the access control to all-supervisor */ asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (~0)); |