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authorWenyou Yang2018-02-09 11:34:50 +0800
committerTom Rini2018-03-16 07:30:04 -0400
commitcb0cb1b0cf20687cf980fbd64c56224f06d566aa (patch)
treefc288310c6acd4c3f6874114b53ba737532b52f7 /arch/arm/mach-at91/include
parent735f397c14b81789dea00a8948b50ef76fa17739 (diff)
clk: at91: add USB Host clock driver
Add USB clock driver to configure the input clock and the divider in the PMC_USB register to generate a 48MHz and a 12MHz signal to the USB Host OHCI. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Diffstat (limited to 'arch/arm/mach-at91/include')
-rw-r--r--arch/arm/mach-at91/include/mach/at91_pmc.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 08ad1bf2d04..fbda8d5f633 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -233,9 +233,15 @@ typedef struct at91_pmc {
#define AT91_PMC_PDIV_1 (0 << 12)
#define AT91_PMC_PDIV_2 (1 << 12)
+#define AT91_PMC_USB_USBS_MASK 0x1
+#define AT91_PMC_USB_USBS_OFFSET 0
+#define AT91_PMC_USB_USBS_(x) (x & 0x1)
#define AT91_PMC_USBS_USB_PLLA (0x0) /* USB Clock Input is PLLA */
#define AT91_PMC_USBS_USB_UPLL (0x1) /* USB Clock Input is UPLL */
#define AT91_PMC_USBS_USB_PLLB (0x1) /* USB Clock Input is PLLB, AT91SAM9N12 only */
+#define AT91_PMC_USB_DIV_MASK 0xf
+#define AT91_PMC_USB_DIV_OFFSET 8
+#define AT91_PMC_USB_DIV_(x) ((x & 0xf) << 8)
#define AT91_PMC_USB_DIV_2 (0x1 << 8) /* USB Clock divided by 2 */
#define AT91_PMC_USBDIV_8 (0x7 << 8) /* USB Clock divided by 8 */
#define AT91_PMC_USBDIV_10 (0x9 << 8) /* USB Clock divided by 10 */