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authorHeiko Schocher2016-08-17 09:13:24 +0200
committerAndreas Bießmann2016-10-28 18:37:13 +0200
commit806a5a3958e4af483e529cf0db75464055d6e13a (patch)
treebf7eab9fca9d4d2c714e538640981d8d6346c263 /arch/arm/mach-at91
parent20e00c13681b69ad7f858a5e28baeb0c6e61c9e6 (diff)
ARM: at91: clock: correct PRES offset for at91sam9x5
on at91sam9x5 PRES offset is 4 in the PMC master clock register. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Andreas Bießmann <andreas@biessmann.org>
Diffstat (limited to 'arch/arm/mach-at91')
-rw-r--r--arch/arm/mach-at91/arm926ejs/clock.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c
index c8d24ae8265..e3181fab84f 100644
--- a/arch/arm/mach-at91/arm926ejs/clock.c
+++ b/arch/arm/mach-at91/arm926ejs/clock.c
@@ -162,7 +162,13 @@ int at91_clock_init(unsigned long main_clock)
gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
freq = gd->arch.mck_rate_hz;
+#if defined(CONFIG_AT91SAM9X5)
+ /* different in prescale on at91sam9x5 */
+ freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 4));
+#else
freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
+#endif
+
#if defined(CONFIG_AT91SAM9G20)
/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?