diff options
| author | Ye Li | 2019-07-22 01:25:08 +0000 |
|---|---|---|
| committer | Stefano Babic | 2019-10-08 16:35:16 +0200 |
| commit | df3572e93033d7620767ed6dc9790dceb110636c (patch) | |
| tree | ba283913b49212aeeb0404a4020d6cd9ba2de576 /arch/arm/mach-imx/mx7ulp/clock.c | |
| parent | e25dc290aa85ea3b68000295e352681acfa53617 (diff) | |
i.MX7ULP: Set A7 core frequency to 500Mhz for B0 chip
The normal target frequency for ULP A7 core is 500Mhz, but now ROM
set the core frequency to 413Mhz. So change it to 500Mhz in u-boot.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx/mx7ulp/clock.c')
| -rw-r--r-- | arch/arm/mach-imx/mx7ulp/clock.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c index 7012157078e..7bf83170eb9 100644 --- a/arch/arm/mach-imx/mx7ulp/clock.c +++ b/arch/arm/mach-imx/mx7ulp/clock.c @@ -300,6 +300,8 @@ void clock_init(void) scg_a7_soscdiv_init(); + scg_a7_init_core_clk(); + /* APLL PFD1 = 270Mhz, PFD2=345.6Mhz, PFD3=800Mhz */ scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35); scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 28); |