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authorAradhya Bhatia2024-02-12 15:36:35 +0530
committerTom Rini2024-03-01 09:15:58 -0500
commit72703c7a0dd8ede6c98d13152fc1ebd3da4bc128 (patch)
tree00792dd20b7d0da8ffc0d973b317b9ef60782c5b /arch/arm/mach-k3/r5
parent8fb8a6d499773a2a06df8152950077985f926c86 (diff)
arm: mach-k3: Refactor QoS settings
Refactor common QoS code into a new common header file, and the soc specific setup_qos functions into a common API. Rename $(soc)_qos_count and $(soc)_qos_data variables to qos_count and qos_data. When QoS settings of more SoCs are added, only one pair will be defined at a time, based on the config SOC_K3_$(soc). This refactoring has been done for 2 major purposes. - The auto-generated $(soc)_qos_data.c and $(soc)_qos.h files cannot have any code that is specific to any bootloader. Those files have to remain agnostic of different bootloader implementations and their header files. - The existing implementation was less than ideal and would have enabled multiple $(soc)_qos_count and $(soc)_qos_data variables for all SoC variants. Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
Diffstat (limited to 'arch/arm/mach-k3/r5')
-rw-r--r--arch/arm/mach-k3/r5/Kconfig8
-rw-r--r--arch/arm/mach-k3/r5/am62ax/Makefile2
-rw-r--r--arch/arm/mach-k3/r5/am62ax/am62a_qos.h114
-rw-r--r--arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c (renamed from arch/arm/mach-k3/r5/am62ax/am62a_qos_data.c)9
4 files changed, 128 insertions, 5 deletions
diff --git a/arch/arm/mach-k3/r5/Kconfig b/arch/arm/mach-k3/r5/Kconfig
index ae79f8ff6cd..940a6dc4f4d 100644
--- a/arch/arm/mach-k3/r5/Kconfig
+++ b/arch/arm/mach-k3/r5/Kconfig
@@ -1,6 +1,14 @@
config K3_LOAD_SYSFW
bool
+config K3_QOS
+ bool "Enable Quality of Service (QoS) Settings for TI K3 SoCs"
+ default y if SOC_K3_AM62A7
+ help
+ This option enables the R5 SPL to apply QoS settings for various
+ HW controllers inside the TI K3 SoCs. The files for QoS settings are
+ generated from Sysconfig and k3-resource-partitioning tools.
+
config K3_SYSFW_IMAGE_NAME
string "File name of SYSFW firmware and configuration blob"
depends on K3_LOAD_SYSFW
diff --git a/arch/arm/mach-k3/r5/am62ax/Makefile b/arch/arm/mach-k3/r5/am62ax/Makefile
index 02a941805e9..e4e55ce5c7d 100644
--- a/arch/arm/mach-k3/r5/am62ax/Makefile
+++ b/arch/arm/mach-k3/r5/am62ax/Makefile
@@ -4,4 +4,4 @@
obj-y += clk-data.o
obj-y += dev-data.o
-obj-y += am62a_qos_data.o
+obj-y += am62a_qos_uboot.o
diff --git a/arch/arm/mach-k3/r5/am62ax/am62a_qos.h b/arch/arm/mach-k3/r5/am62ax/am62a_qos.h
new file mode 100644
index 00000000000..c74d69a28f8
--- /dev/null
+++ b/arch/arm/mach-k3/r5/am62ax/am62a_qos.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define QOS_0 (0 << 0)
+#define QOS_1 (1 << 0)
+#define QOS_2 (2 << 0)
+#define QOS_3 (3 << 0)
+#define QOS_4 (4 << 0)
+#define QOS_5 (5 << 0)
+#define QOS_6 (6 << 0)
+#define QOS_7 (7 << 0)
+
+#define ORDERID_0 (0 << 4)
+#define ORDERID_1 (1 << 4)
+#define ORDERID_2 (2 << 4)
+#define ORDERID_3 (3 << 4)
+#define ORDERID_4 (4 << 4)
+#define ORDERID_5 (5 << 4)
+#define ORDERID_6 (6 << 4)
+#define ORDERID_7 (7 << 4)
+#define ORDERID_8 (8 << 4)
+#define ORDERID_9 (9 << 4)
+#define ORDERID_10 (10 << 4)
+#define ORDERID_11 (11 << 4)
+#define ORDERID_12 (12 << 4)
+#define ORDERID_13 (13 << 4)
+#define ORDERID_14 (14 << 4)
+#define ORDERID_15 (15 << 4)
+
+#define ASEL_0 (0 << 8)
+#define ASEL_1 (1 << 8)
+#define ASEL_2 (2 << 8)
+#define ASEL_3 (3 << 8)
+#define ASEL_4 (4 << 8)
+#define ASEL_5 (5 << 8)
+#define ASEL_6 (6 << 8)
+#define ASEL_7 (7 << 8)
+#define ASEL_8 (8 << 8)
+#define ASEL_9 (9 << 8)
+#define ASEL_10 (10 << 8)
+#define ASEL_11 (11 << 8)
+#define ASEL_12 (12 << 8)
+#define ASEL_13 (13 << 8)
+#define ASEL_14 (14 << 8)
+#define ASEL_15 (15 << 8)
+
+#define EPRIORITY_0 (0 << 12)
+#define EPRIORITY_1 (1 << 12)
+#define EPRIORITY_2 (2 << 12)
+#define EPRIORITY_3 (3 << 12)
+#define EPRIORITY_4 (4 << 12)
+#define EPRIORITY_5 (5 << 12)
+#define EPRIORITY_6 (6 << 12)
+#define EPRIORITY_7 (7 << 12)
+
+#define VIRTID_0 (0 << 16)
+#define VIRTID_1 (1 << 16)
+#define VIRTID_2 (2 << 16)
+#define VIRTID_3 (3 << 16)
+#define VIRTID_4 (4 << 16)
+#define VIRTID_5 (5 << 16)
+#define VIRTID_6 (6 << 16)
+#define VIRTID_7 (7 << 16)
+#define VIRTID_8 (8 << 16)
+#define VIRTID_9 (9 << 16)
+#define VIRTID_10 (10 << 16)
+#define VIRTID_11 (11 << 16)
+#define VIRTID_12 (12 << 16)
+#define VIRTID_13 (13 << 16)
+#define VIRTID_14 (14 << 16)
+#define VIRTID_15 (15 << 16)
+
+#define ATYPE_0 (0 << 28)
+#define ATYPE_1 (1 << 28)
+#define ATYPE_2 (2 << 28)
+#define ATYPE_3 (3 << 28)
+
+#define PULSAR_UL_WKUP_0_CPU0_RMST 0x45D14000
+#define PULSAR_UL_WKUP_0_CPU0_WMST 0x45D14400
+#define PULSAR_UL_WKUP_0_CPU0_PMST 0x45D14800
+#define PULSAR_ULS_MCU_0_CPU0_RMST 0x45D18000
+#define PULSAR_ULS_MCU_0_CPU0_WMST 0x45D18400
+#define PULSAR_ULS_MCU_0_CPU0_PMST 0x45D18800
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_R 0x45D20400
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_W 0x45D20800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45D21800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45D21C00
+#define GIC500SS_1_4_MAIN_0_MEM_WR_VBUSM 0x45D22000
+#define GIC500SS_1_4_MAIN_0_MEM_RD_VBUSM 0x45D22400
+#define EMMCSD8SS_MAIN_0_EMMCSDSS_RD 0x45D22800
+#define EMMCSD8SS_MAIN_0_EMMCSDSS_WR 0x45D22C00
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D23000
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D23400
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR 0x45D23800
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD 0x45D23C00
+#define USB2SS_16FFC_MAIN_0_MSTW0 0x45D24000
+#define USB2SS_16FFC_MAIN_0_MSTR0 0x45D24400
+#define USB2SS_16FFC_MAIN_1_MSTR0 0x45D24800
+#define USB2SS_16FFC_MAIN_1_MSTW0 0x45D24C00
+#define K3_DSS_UL_MAIN_0_VBUSM_DMA 0x45D25000
+#define SA3SS_AM62A_MAIN_0_CTXCACH_EXT_DMA 0x45D25400
+#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_W 0x45D25800
+#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_R 0x45D25C00
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45D26800
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45D26C00
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45D27000
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45D27400
+#define SAM62A_C7XV_WRAP_MAIN_0_C7XV_SOC 0x45D27800
+#define SAM62A_VPAC_WRAP_MAIN_0_LDC0_M_MST 0x45D28000
diff --git a/arch/arm/mach-k3/r5/am62ax/am62a_qos_data.c b/arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c
index 38db4f2f5c8..9a82944d5fe 100644
--- a/arch/arm/mach-k3/r5/am62ax/am62a_qos_data.c
+++ b/arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c
@@ -5,10 +5,11 @@
*
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
-#include <asm/arch/hardware.h>
-#include "common.h"
-struct k3_qos_data am62a_qos_data[] = {
+#include <asm/arch/k3-qos.h>
+#include "am62a_qos.h"
+
+struct k3_qos_data qos_data[] = {
/* modules_qosConfig0 - 1 endpoints, 4 channels */
{
.reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 0,
@@ -43,4 +44,4 @@ struct k3_qos_data am62a_qos_data[] = {
},
};
-uint32_t am62a_qos_count = sizeof(am62a_qos_data) / sizeof(am62a_qos_data[0]);
+u32 qos_count = ARRAY_SIZE(qos_data);