diff options
author | Stefan Roese | 2015-04-25 06:29:51 +0200 |
---|---|---|
committer | Luka Perkov | 2015-05-05 14:28:29 +0200 |
commit | 9c6d3b7b666b949a5015146a6539b468fbbf451f (patch) | |
tree | 337073ad3b6e4488b4aa56542cbdfedf94e68ae8 /arch/arm/mach-mvebu/cpu.c | |
parent | 880b15a37b22ce516b24460e4bbedd9a6b055625 (diff) |
arm: mvebu: Add basic Armada 38x support
This patch adds support for the Marvell Armada 38x SoC family.
Supported peripherals are:
- UART
- Ethernet (mvneta)
- I2C
- SPI (including SPI NOR flash)
Tested on Marvell DB-88F6820-GP evaluation board.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Diffstat (limited to 'arch/arm/mach-mvebu/cpu.c')
-rw-r--r-- | arch/arm/mach-mvebu/cpu.c | 73 |
1 files changed, 57 insertions, 16 deletions
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 1cf70a9f5d5..eca5e2176cd 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -40,6 +40,20 @@ void reset_cpu(unsigned long ignored) ; } +int mvebu_soc_family(void) +{ + u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; + + if (devid == SOC_MV78460_ID) + return MVEBU_SOC_AXP; + + if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID || + devid == SOC_88F6828_ID) + return MVEBU_SOC_A38X; + + return MVEBU_SOC_UNKNOWN; +} + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { @@ -52,23 +66,48 @@ int print_cpuinfo(void) case SOC_MV78460_ID: puts("MV78460-"); break; - default: - puts("Unknown-"); + case SOC_88F6810_ID: + puts("MV88F6810-"); break; - } - - switch (revid) { - case 1: - puts("A0\n"); + case SOC_88F6820_ID: + puts("MV88F6820-"); break; - case 2: - puts("B0\n"); + case SOC_88F6828_ID: + puts("MV88F6828-"); break; default: - puts("??\n"); + puts("Unknown-"); break; } + if (mvebu_soc_family() == MVEBU_SOC_AXP) { + switch (revid) { + case 1: + puts("A0\n"); + break; + case 2: + puts("B0\n"); + break; + default: + printf("?? (%x)\n", revid); + break; + } + } + + if (mvebu_soc_family() == MVEBU_SOC_A38X) { + switch (revid) { + case MV_88F68XX_Z1_ID: + puts("Z1\n"); + break; + case MV_88F68XX_A0_ID: + puts("A0\n"); + break; + default: + printf("?? (%x)\n", revid); + break; + } + } + return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ @@ -145,11 +184,13 @@ int arch_cpu_init(void) */ mvebu_mbus_probe(NULL, 0); - /* - * Now the SDRAM access windows can be reconfigured using - * the information in the SDRAM scratch pad registers - */ - update_sdram_window_sizes(); + if (mvebu_soc_family() == MVEBU_SOC_AXP) { + /* + * Now the SDRAM access windows can be reconfigured using + * the information in the SDRAM scratch pad registers + */ + update_sdram_window_sizes(); + } /* * Finally the mbus windows can be configured with the |