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authorChris Packham2020-06-25 12:48:51 +1200
committerStefan Roese2020-07-09 06:49:44 +0200
commit4182232158bfff7363fa0b4eade360cf50551cb9 (patch)
tree8685c0cf92620f8c982a7568097ec80027fc1cbd /arch/arm/mach-mvebu
parentec9deec40032821a2ea17fbc503a48c6f8619589 (diff)
arm: mvebu: a38x: Adjust UTMI PHY parameters
When running USB compliance tests on our Armada-385 hardware platforms we have seen some eye mask violations. Marvell's internal documentation says: Based on silicon test results, it is recommended to change the impedance calibration threshold setting to 0x6 prior to calibration. Port changes from Marvell's u-boot fork[1] to address this. [1] - https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/a6221551 Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/arm/mach-mvebu')
-rw-r--r--arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c25
1 files changed, 21 insertions, 4 deletions
diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
index d4480622c89..2454730e6d8 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
@@ -672,12 +672,29 @@ struct op_params usb2_power_up_params[] = {
{0xc200c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0},
/* Phy0 register 3 - TX Channel control 0 */
{0xc400c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0},
- /* check PLLCAL_DONE is set and IMPCAL_DONE is set */
+ /* Decrease the amplitude of the low speed eye to meet the spec */
+ {0xc000c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0},
+ {0xc200c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0},
+ {0xc400c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0},
+ /* Change the High speed impedance threshold */
+ {0xc0008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0},
+ {0xc2008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0},
+ {0xc4008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0},
+ /* Change the squelch level of the receiver to meet the receiver electrical measurements (squelch and receiver sensitivity tests) */
+ {0xc0014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0},
+ {0xc2014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0},
+ {0xc4014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0},
+ /* Check PLLCAL_DONE is set and IMPCAL_DONE is set */
{0xc0008, 0x0 /*NA*/, 0x80800000, {0x80800000}, 1, 1000},
- /* check REG_SQCAL_DONE is set */
+ /* Check REG_SQCAL_DONE is set */
{0xc0018, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000},
- /* check PLL_READY is set */
- {0xc0000, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000}
+ /* Check PLL_READY is set */
+ {0xc0000, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000},
+ /* Start calibrate of high seed impedance */
+ {0xc0008, 0x0 /*NA*/, 0x2000, {0x2000}, 0, 0},
+ {0x0, 0x0 /*NA*/, 0x0, {0x0}, 10, 0},
+ /* De-assert the calibration signal */
+ {0xc0008, 0x0 /*NA*/, 0x2000, {0x0}, 0, 0},
};
/*