diff options
| author | Nobuhiro Iwamatsu | 2016-08-04 14:10:26 +0900 |
|---|---|---|
| committer | Nobuhiro Iwamatsu | 2016-08-17 10:25:36 +0900 |
| commit | 798dc6be7feabce33676877f85d307f571a9ec15 (patch) | |
| tree | 3914c7206d7f1798d5bf91cb4630b25fe6481635 /arch/arm/mach-rmobile | |
| parent | 544661bdbf12b2f0d23101404c89565df2ffaffb (diff) | |
ARM: rmobile: r8a7795: Add MMU layout
This add MMU layout for R8A7795 of Renesas ARM64 SoC.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'arch/arm/mach-rmobile')
| -rw-r--r-- | arch/arm/mach-rmobile/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/mach-rmobile/memmap-r8a7795.c | 30 |
2 files changed, 31 insertions, 1 deletions
diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile index d5bb8433087..3b56fcf96f8 100644 --- a/arch/arm/mach-rmobile/Makefile +++ b/arch/arm/mach-rmobile/Makefile @@ -16,6 +16,6 @@ obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7792.o obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o -obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7795.o +obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7795.o memmap-r8a7795.o obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o diff --git a/arch/arm/mach-rmobile/memmap-r8a7795.c b/arch/arm/mach-rmobile/memmap-r8a7795.c new file mode 100644 index 00000000000..c2c5e48aaf7 --- /dev/null +++ b/arch/arm/mach-rmobile/memmap-r8a7795.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2016 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/armv8/mmu.h> + +static struct mm_region r8a7795_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = r8a7795_mem_map; |