diff options
| author | Jit Loon Lim | 2024-03-12 22:01:03 +0800 |
|---|---|---|
| committer | Tien Fong Chee | 2024-03-18 14:45:47 +0800 |
| commit | 386fca68960994ece0d9da8a69a14495b5f1aedf (patch) | |
| tree | 880c6d852446a8fdcb47184986f92bb2812a2a6a /arch/arm/mach-socfpga/Makefile | |
| parent | 3f190c55a4211215914126b74357344342329943 (diff) | |
arch: arm: Agilex5 enablement
This patch is to enable Agilex5 platform for Intel
product. Changes, modification and new files are
created for board, dts, configs and makefile to
create the base for Agilex5.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
Diffstat (limited to 'arch/arm/mach-socfpga/Makefile')
| -rw-r--r-- | arch/arm/mach-socfpga/Makefile | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index ec38b64dd4d..67c6a8dfec5 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -4,7 +4,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # Copyright (C) 2012-2017 Altera Corporation <www.altera.com> -# Copyright (C) 2017-2021 Intel Corporation <www.intel.com> +# Copyright (C) 2017-2024 Intel Corporation <www.intel.com> obj-y += board.o obj-y += clock_manager.o @@ -56,6 +56,15 @@ obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 +obj-y += clock_manager_agilex5.o +obj-y += mailbox_s10.o +obj-y += misc_soc64.o +obj-y += mmu-arm64_s10.o +obj-y += reset_manager_s10.o +obj-y += wrap_pll_config_soc64.o +endif + ifdef CONFIG_TARGET_SOCFPGA_N5X obj-y += clock_manager_n5x.o obj-y += lowlevel_init_soc64.o @@ -95,6 +104,9 @@ endif ifdef CONFIG_TARGET_SOCFPGA_N5X obj-y += spl_n5x.o endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 +obj-y += spl_soc64.o +endif else obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o obj-$(CONFIG_SPL_ATF) += smc_api.o |