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authorMarek Vasut2018-05-08 20:32:01 +0200
committerMarek Vasut2019-03-09 17:59:13 +0100
commit7544ad0303013e625c9500a4d87d4e5bfe369ee4 (patch)
tree154edeedce6b844c79ee7aaa325f5f51d6e03b0e /arch/arm/mach-socfpga
parentdc3249b91b0c5dffdbd42426a3535bea5e14448f (diff)
ARM: socfpga: Disable D cache in SPL
The bootrom seems to leave the D-cache in messed up state, make sure the SPL disables it so it can not interfere with operation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Diffstat (limited to 'arch/arm/mach-socfpga')
-rw-r--r--arch/arm/mach-socfpga/spl_a10.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index c97eacb424f..c8e73d47c0b 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -77,6 +77,8 @@ void spl_board_init(void)
void board_init_f(ulong dummy)
{
+ dcache_disable();
+
socfpga_init_security_policies();
socfpga_sdram_remap_zero();