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authorJernej Skrabec2022-01-30 15:27:13 +0100
committerAndre Przywara2022-04-04 23:24:17 +0100
commit1772771ac00150c474a0936f675dc553f44be549 (patch)
treea9eb67f44c127faf83bf4f0fbd6de3ed7168e059 /arch/arm/mach-sunxi
parent482c1ccd1ce450f8c56a891f4067a6db8fb499fd (diff)
sunxi: prcm: Add a few registers
H6 and H616 SPL code has a few writes to unknown PRCM registers. Now that we know what they are, let's replace magic offsets with proper register names. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'arch/arm/mach-sunxi')
-rw-r--r--arch/arm/mach-sunxi/clock_sun50i_h6.c4
-rw-r--r--arch/arm/mach-sunxi/dram_sun50i_h6.c8
-rw-r--r--arch/arm/mach-sunxi/dram_sun50i_h616.c7
3 files changed, 13 insertions, 6 deletions
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index a947463e0a5..e5846e6381f 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -9,10 +9,12 @@ void clock_init_safe(void)
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_prcm_reg *const prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
/* this seems to enable PLLs on H616 */
if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
- setbits_le32(SUNXI_PRCM_BASE + 0x250, 0x10);
+ setbits_le32(&prcm->sys_pwroff_gating, 0x10);
clock_set_pll1(408000000);
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index d05375c9027..b332f3a3e4a 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -12,6 +12,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/dram.h>
#include <asm/arch/cpu.h>
+#include <asm/arch/prcm.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/kconfig.h>
@@ -665,6 +666,8 @@ unsigned long sunxi_dram_init(void)
{
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_prcm_reg *const prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
struct dram_para para = {
.clk = CONFIG_DRAM_CLK,
#ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
@@ -680,9 +683,8 @@ unsigned long sunxi_dram_init(void)
unsigned long size;
- /* RES_CAL_CTRL_REG in BSP U-boot*/
- setbits_le32(0x7010310, BIT(8));
- clrbits_le32(0x7010318, 0x3f);
+ setbits_le32(&prcm->res_cal_ctrl, BIT(8));
+ clrbits_le32(&prcm->ohms240, 0x3f);
mctl_auto_detect_rank_width(&para);
mctl_auto_detect_dram_size(&para);
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 83e8abc2f8d..454c845a001 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -19,6 +19,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/dram.h>
#include <asm/arch/cpu.h>
+#include <asm/arch/prcm.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/kconfig.h>
@@ -1001,14 +1002,16 @@ static unsigned long mctl_calc_size(struct dram_para *para)
unsigned long sunxi_dram_init(void)
{
+ struct sunxi_prcm_reg *const prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
struct dram_para para = {
.clk = CONFIG_DRAM_CLK,
.type = SUNXI_DRAM_TYPE_DDR3,
};
unsigned long size;
- setbits_le32(0x7010310, BIT(8));
- clrbits_le32(0x7010318, 0x3f);
+ setbits_le32(&prcm->res_cal_ctrl, BIT(8));
+ clrbits_le32(&prcm->ohms240, 0x3f);
mctl_auto_detect_rank_width(&para);
mctl_auto_detect_dram_size(&para);