i2c: Add a DM_I2C driver for the sun6i P2WI controller

This bus controller is used to communicate with an X-Powers AXP PMIC.
Currently, various drivers access PMIC registers through a platform-
specific non-DM "pmic_bus" interface, which depends on the legacy I2C
framework. In order to convert those drivers to use DM_PMIC, this bus
needs a DM_I2C driver.

Refactor the p2wi functions to take the base address as a parameter,
and implement both the existing interface (which is still needed in
SPL) and the DM_I2C interface on top of them.

The register for switching between I2C/P2WI/RSB mode is the same across
all PMIC variants. Move that to the common header, so it can be used by
both interface implementations.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

4 files changed, 5 insertions, 134 deletions

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index da35cc87e85..f4a45284bdc 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -88,17 +88,6 @@ config DRAM_SUN50I_H616_UNKNOWN_FEATURE
 	  feature.
 endif
 
-config SUN6I_P2WI
-	bool "Allwinner sun6i internal P2WI controller"
-	help
-	  If you say yes to this option, support will be included for the
-	  P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
-	  SOCs.
-	  The P2WI looks like an SMBus controller (which supports only byte
-	  accesses), except that it only supports one slave device.
-	  This interface is used to connect to specific PMIC devices (like the
-	  AXP221).
-
 config SUN6I_PRCM
 	bool
 	help
@@ -232,10 +221,11 @@ config MACH_SUN6I
 	select ARCH_SUPPORT_PSCI
 	select DRAM_SUN6I
 	select PHY_SUN4I_USB
-	select SUN6I_P2WI
+	select SPL_I2C
 	select SUN6I_PRCM
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
+	select SYS_I2C_SUN6I_P2WI
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
 config MACH_SUN7I
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 3f081d92f37..c9312bb3934 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -11,7 +11,6 @@ obj-y	+= clock.o
 obj-y	+= cpu_info.o
 obj-y	+= dram_helpers.o
 obj-y	+= pinmux.o
-obj-$(CONFIG_SUN6I_P2WI)	+= p2wi.o
 obj-$(CONFIG_SUN6I_PRCM)	+= prcm.o
 obj-$(CONFIG_AXP_PMIC_BUS)	+= pmic_bus.o
 obj-$(CONFIG_SUN8I_RSB)		+= rsb.o
diff --git a/arch/arm/mach-sunxi/p2wi.c b/arch/arm/mach-sunxi/p2wi.c
deleted file mode 100644
index 7c5c12254ea..00000000000
--- a/arch/arm/mach-sunxi/p2wi.c
+++ /dev/null
@@ -1,117 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Sunxi A31 Power Management Unit
- *
- * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
- * http://linux-sunxi.org
- *
- * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work
- *
- * (C) Copyright 2006-2013
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Berg Xing <bergxing@allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
- */
-
-#include <common.h>
-#include <errno.h>
-#include <time.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/p2wi.h>
-#include <asm/arch/prcm.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-
-void p2wi_init(void)
-{
-	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
-
-	/* Enable p2wi and PIO clk, and de-assert their resets */
-	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
-
-	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
-	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
-
-	/* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
-	writel(P2WI_CTRL_RESET, &p2wi->ctrl);
-	sdelay(0x100);
-	writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
-	       &p2wi->cc);
-}
-
-int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
-{
-	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
-	unsigned long tmo = timer_get_us() + 1000000;
-
-	writel(P2WI_PM_DEV_ADDR(slave_addr) |
-	       P2WI_PM_CTRL_ADDR(ctrl_reg) |
-	       P2WI_PM_INIT_DATA(init_data) |
-	       P2WI_PM_INIT_SEND,
-	       &p2wi->pm);
-
-	while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) {
-		if (timer_get_us() > tmo)
-			return -ETIME;
-	}
-
-	return 0;
-}
-
-static int p2wi_await_trans(void)
-{
-	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
-	unsigned long tmo = timer_get_us() + 1000000;
-	int ret;
-	u8 reg;
-
-	while (1) {
-		reg = readl(&p2wi->status);
-		if (reg & P2WI_STAT_TRANS_ERR) {
-			ret = -EIO;
-			break;
-		}
-		if (reg & P2WI_STAT_TRANS_DONE) {
-			ret = 0;
-			break;
-		}
-		if (timer_get_us() > tmo) {
-			ret = -ETIME;
-			break;
-		}
-	}
-	writel(reg, &p2wi->status); /* Clear status bits */
-	return ret;
-}
-
-int p2wi_read(const u8 addr, u8 *data)
-{
-	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
-	int ret;
-
-	writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
-	writel(P2WI_DATA_NUM_BYTES(1) |
-	       P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes);
-	writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
-	writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
-
-	ret = p2wi_await_trans();
-
-	*data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK;
-	return ret;
-}
-
-int p2wi_write(const u8 addr, u8 data)
-{
-	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
-
-	writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
-	writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);
-	writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes);
-	writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
-	writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
-
-	return p2wi_await_trans();
-}
diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c
index 0394ce85644..673a05fdd16 100644
--- a/arch/arm/mach-sunxi/pmic_bus.c
+++ b/arch/arm/mach-sunxi/pmic_bus.c
@@ -8,6 +8,7 @@
  * axp223 uses the rsb bus, these functions abstract this.
  */
 
+#include <axp_pmic.h>
 #include <common.h>
 #include <asm/arch/p2wi.h>
 #include <asm/arch/rsb.h>
@@ -21,8 +22,6 @@
 #define AXP305_I2C_ADDR			0x36
 
 #define AXP221_CHIP_ADDR		0x68
-#define AXP221_CTRL_ADDR		0x3e
-#define AXP221_INIT_DATA		0x3e
 
 /* AXP818 device and runtime addresses are same as AXP223 */
 #define AXP223_DEVICE_ADDR		0x3a3
@@ -40,8 +39,8 @@ int pmic_bus_init(void)
 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
 	p2wi_init();
-	ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
-				       AXP221_INIT_DATA);
+	ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP_PMIC_MODE_REG,
+				       AXP_PMIC_MODE_P2WI);
 # elif defined CONFIG_MACH_SUN8I_R40
 	/* Nothing. R40 uses the AXP221s in I2C mode */
 	ret = 0;