diff options
| author | Vladimir Zapolskiy | 2015-10-04 23:18:45 +0100 |
|---|---|---|
| committer | Tom Rini | 2015-10-11 17:12:13 -0400 |
| commit | 4c90234586833c0bb4a5d9d3f69a69c8ab09e01f (patch) | |
| tree | 2ac2373905fe23b18d4c4eddc897de6664bc842b /arch/arm | |
| parent | f0aa26f006339969d5e712c50fdb6838333be3b8 (diff) | |
lpc32xx: fix calculation of HCLK PLL output clock
Execution branches on feedback mode are swapped, this has no effect
if default direct mode is on (then p_div is equal to 1 and Fout equals
to Fcco), that's why the problem remained unnoticed for a long time.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c index 1ef8a366696..f5e2103426e 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c @@ -54,12 +54,12 @@ unsigned int get_hclk_pll_rate(void) if (fref > 27000000ULL || fref < 1000000ULL) return 0; - fout = fref * m_div; - if (val & CLK_HCLK_PLL_FEEDBACK) { - fcco = fout; + fcco = fref * m_div; + fout = fcco; + if (val & CLK_HCLK_PLL_FEEDBACK) + fcco *= p_div; + else do_div(fout, p_div); - } else - fcco = fout * p_div; if (fcco > 320000000ULL || fcco < 156000000ULL) return 0; |