diff options
| author | Ye Li | 2022-04-06 14:30:14 +0800 |
|---|---|---|
| committer | Stefano Babic | 2022-04-12 17:33:56 +0200 |
| commit | 509b8e7ba13a7c262fb673fbf77a997977b14991 (patch) | |
| tree | 3af461cf79abb5eff3e251b43327e15360161834 /arch/arm | |
| parent | 4ab38f6822d9564da7b85649e6bc7d5c9d603350 (diff) | |
imx: imx8ulp: cgc: Switch to NICLPAV to FRO192 before PLL4 init
When reset with dual boot mode, the LPAV domain won't power down
due to its master is not assigned to APD. So the NICLPAV keeps the
last setting to use PLL4PFD1. So before SPL initialize the PLL4,
we need to switch NICLPAV to FRO192, otherwise system will hang.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-imx/imx8ulp/cgc.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c index ccd977f1a5d..d240abaee46 100644 --- a/arch/arm/mach-imx/imx8ulp/cgc.c +++ b/arch/arm/mach-imx/imx8ulp/cgc.c @@ -189,6 +189,14 @@ void cgc1_pll3_init(ulong freq) void cgc2_pll4_init(bool pll4_reset) { + /* Check the NICLPAV first to ensure not from PLL4 PFD1 clock */ + if ((readl(&cgc2_regs->niclpavclk) & GENMASK(29, 28)) == BIT(28)) { + /* switch to FRO 192 first */ + clrbits_le32(&cgc2_regs->niclpavclk, GENMASK(29, 28)); + while (!(readl(&cgc2_regs->niclpavclk) & BIT(27))) + ; + } + /* Disable PFD DIV and clear DIV */ writel(0x80808080, &cgc2_regs->pll4div_pfd0); writel(0x80808080, &cgc2_regs->pll4div_pfd1); |