Merge tag 'u-boot-stm32-mcu-20190423' of https://github.com/pchotard/u-boot

STM32 MCUs update: - DT rework and alignment with DT kernel v4.20 - mmc: arm_pl180_mmci: Synchronize compatible with kernel v4.20 - mmc: stm32_sdmmc2: Synchronize properties with kernel v4.20 - configs: update for F746/769 boards
author: Tom Rini 2019-04-24 12:26:39 -0400
committer: Tom Rini 2019-04-24 12:26:39 -0400
commit: c2bb9c5b9e333c200e3702d9ed5ac9b6095191b6 (patch)
tree: f3a017fe861211d45c8965aeac2f488f06c989d5 /arch/arm
parent: ceb6ddbc73607e9395bb5f0ad94159755f049e77 (diff)
parent: c406a474311c1ee3c4303a7e85db4a8e45966e31 (diff)
28 files changed, 2625 insertions, 1127 deletions
diff --git a/arch/arm/dts/stm32746g-eval-u-boot.dtsi b/arch/arm/dts/stm32746g-eval-u-boot.dtsi
new file mode 100644
index 00000000000..9b55bb7601b
--- /dev/null
+++ b/arch/arm/dts/stm32746g-eval-u-boot.dtsi
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <stm32f7-u-boot.dtsi>
+/{
+	chosen {
+		bootargs = "root=/dev/mmcblk0p1 rw rootwait";
+	};
+
+	aliases {
+		/* Aliases for gpios so as to use sequence */
+		gpio0 = &gpioa;
+		gpio1 = &gpiob;
+		gpio2 = &gpioc;
+		gpio3 = &gpiod;
+		gpio4 = &gpioe;
+		gpio5 = &gpiof;
+		gpio6 = &gpiog;
+		gpio7 = &gpioh;
+		gpio8 = &gpioi;
+		gpio9 = &gpioj;
+		gpio10 = &gpiok;
+		mmc0 = &sdio1;
+		spi0 = &qspi;
+	};
+
+	button1 {
+		compatible = "st,button1";
+		button-gpio = <&gpioc 13 0>;
+	};
+
+	led1 {
+		compatible = "st,led1";
+		led-gpio = <&gpiof 10 0>;
+	};
+};
+
+&fmc {
+	/*
+	 * Memory configuration from sdram datasheet IS42S32800G-6BLI
+	 */
+	bank1: bank@0 {
+		u-boot,dm-pre-reloc;
+		st,sdram-control = /bits/ 8 <NO_COL_9
+					     NO_ROW_12
+					     MWIDTH_32
+					     BANKS_4
+					     CAS_2
+					     SDCLK_3
+					     RD_BURST_EN
+					     RD_PIPE_DL_0>;
+		st,sdram-timing = /bits/ 8 <TMRD_1
+					    TXSR_1
+					    TRAS_1
+					    TRC_6
+					    TRP_2
+					    TWR_1
+					    TRCD_1>;
+		st,sdram-refcount = <1539>;
+	};
+};
+
+&mac {
+	phy-mode = "mii";
+};
+
+&pinctrl {
+	ethernet_mii: mii@0 {
+		pins {
+			pinmux = <STM32_PINMUX('A', 0, AF11)>, /*ETH_MII_CRS */
+				 <STM32_PINMUX('A', 1, AF11)>, /*ETH_MII_RX_CLK */
+				 <STM32_PINMUX('A', 7, AF11)>, /*ETH_MII_RX_DV */
+				 <STM32_PINMUX('A', 8, AF0)>, /*ETH_MII_MCO1 */
+				 <STM32_PINMUX('G',13, AF11)>, /*ETH_MII_TXD0 */
+				 <STM32_PINMUX('G',14, AF11)>, /*ETH_MII_TXD1 */
+				 <STM32_PINMUX('C', 2, AF11)>, /*ETH_MII_TXD2 */
+				 <STM32_PINMUX('E', 2, AF11)>, /*ETH_MII_TXD3 */
+				 <STM32_PINMUX('C', 3, AF11)>, /*ETH_MII_TX_CLK */
+				 <STM32_PINMUX('C', 4, AF11)>, /*ETH_MII_RXD0 */
+				 <STM32_PINMUX('C', 5, AF11)>, /*ETH_MII_RXD1 */
+				 <STM32_PINMUX('H', 6, AF11)>, /*ETH_MII_RXD2 */
+				 <STM32_PINMUX('H', 7, AF11)>, /*ETH_MII_RXD3 */
+				 <STM32_PINMUX('G',11, AF11)>, /*ETH_MII_TX_EN */
+				 <STM32_PINMUX('C', 1, AF11)>, /*ETH_MII_MDC */
+				 <STM32_PINMUX('A', 2, AF11)>; /*ETH_MII_MDIO */
+			slew-rate = <2>;
+		};
+	};
+
+	fmc_pins: fmc@0 {
+		pins {
+			pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
+				 <STM32_PINMUX('I', 9, AF12)>, /* D30 */
+				 <STM32_PINMUX('I', 7, AF12)>, /* D29 */
+				 <STM32_PINMUX('I', 6, AF12)>, /* D28 */
+				 <STM32_PINMUX('I', 3, AF12)>, /* D27 */
+				 <STM32_PINMUX('I', 2, AF12)>, /* D26 */
+				 <STM32_PINMUX('I', 1, AF12)>, /* D25 */
+				 <STM32_PINMUX('I', 0, AF12)>, /* D24 */
+				 <STM32_PINMUX('H',15, AF12)>, /* D23 */
+				 <STM32_PINMUX('H',14, AF12)>, /* D22 */
+				 <STM32_PINMUX('H',13, AF12)>, /* D21 */
+				 <STM32_PINMUX('H',12, AF12)>, /* D20 */
+				 <STM32_PINMUX('H',11, AF12)>, /* D19 */
+				 <STM32_PINMUX('H',10, AF12)>, /* D18 */
+				 <STM32_PINMUX('H', 9, AF12)>, /* D17 */
+				 <STM32_PINMUX('H', 8, AF12)>, /* D16 */
+
+				 <STM32_PINMUX('D',10, AF12)>, /* D15 */
+				 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
+				 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
+				 <STM32_PINMUX('E',15, AF12)>, /* D12 */
+				 <STM32_PINMUX('E',14, AF12)>, /* D11 */
+				 <STM32_PINMUX('E',13, AF12)>, /* D10 */
+				 <STM32_PINMUX('E',12, AF12)>, /* D9 */
+				 <STM32_PINMUX('E',11, AF12)>, /* D8 */
+				 <STM32_PINMUX('E',10, AF12)>, /* D7 */
+				 <STM32_PINMUX('E', 9, AF12)>, /* D6 */
+				 <STM32_PINMUX('E', 8, AF12)>, /* D5 */
+				 <STM32_PINMUX('E', 7, AF12)>, /* D4 */
+				 <STM32_PINMUX('D', 1, AF12)>, /* D3 */
+				 <STM32_PINMUX('D', 0, AF12)>, /* D2 */
+				 <STM32_PINMUX('D',15, AF12)>, /* D1 */
+				 <STM32_PINMUX('D',14, AF12)>, /* D0 */
+
+				 <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
+				 <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
+				 <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
+				 <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
+
+				 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
+				 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
+
+				 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
+				 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
+				 <STM32_PINMUX('F',15, AF12)>, /* A9 */
+				 <STM32_PINMUX('F',14, AF12)>, /* A8 */
+				 <STM32_PINMUX('F',13, AF12)>, /* A7 */
+				 <STM32_PINMUX('F',12, AF12)>, /* A6 */
+				 <STM32_PINMUX('F', 5, AF12)>, /* A5 */
+				 <STM32_PINMUX('F', 4, AF12)>, /* A4 */
+				 <STM32_PINMUX('F', 3, AF12)>, /* A3 */
+				 <STM32_PINMUX('F', 2, AF12)>, /* A2 */
+				 <STM32_PINMUX('F', 1, AF12)>, /* A1 */
+				 <STM32_PINMUX('F', 0, AF12)>, /* A0 */
+
+				 <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
+				 <STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
+				 <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
+				 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
+				 <STM32_PINMUX('C', 3, AF12)>, /* SDCKE0 */
+				 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
+			slew-rate = <2>;
+		};
+	};
+
+	qspi_pins: qspi@0 {
+		pins {
+			pinmux = <STM32_PINMUX('B', 2, AF9)>, /* _FUNC_QUADSPI_CLK */
+				 <STM32_PINMUX('B', 6, AF10)>, /*_FUNC_QUADSPI_BK1_NCS */
+				 <STM32_PINMUX('F', 8, AF10)>, /* _FUNC_QUADSPI_BK1_IO0 */
+				 <STM32_PINMUX('F', 9, AF10)>, /* _FUNC_QUADSPI_BK1_IO1 */
+				 <STM32_PINMUX('F', 6, AF9)>, /* AF_FUNC_QUADSPI_BK1_IO3 */
+				 <STM32_PINMUX('F', 7, AF9)>; /* _FUNC_QUADSPI_BK1_IO2 */
+			slew-rate = <2>;
+		};
+	};
+
+	usart1_pins_a: usart1@0	{
+		u-boot,dm-pre-reloc;
+		pins1 {
+			u-boot,dm-pre-reloc;
+		};
+		pins2 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
+
+&qspi {
+	qflash0: n25q512a {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <108000000>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+		reg = <0>;
+	};
+};
diff --git a/arch/arm/dts/stm32746g-eval.dts b/arch/arm/dts/stm32746g-eval.dts
index 4f6d38acccd..8c081eaf20f 100644
--- a/arch/arm/dts/stm32746g-eval.dts
+++ b/arch/arm/dts/stm32746g-eval.dts
@@ -1,9 +1,5 @@
 /*
- * Copyright 2018 - Christophe Priouzeau <christophe.priouzeau@st.com>
- *
- * Based on:
- * stm32f746-disco.dts from U-boot 2018.01
- * Copyright 2016 - Lee Jones <lee.jones@linaro.org>
+ * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -46,47 +42,61 @@
 
 /dts-v1/;
 #include "stm32f746.dtsi"
-#include <dt-bindings/memory/stm32-sdram.h>
+#include "stm32f746-pinctrl.dtsi"
+#include <dt-bindings/input/input.h>
 
 / {
-	model = "STMicroelectronics STM32F746G-EVAL board";
-	compatible = "st,stm32f746g-eval", "st,stm32f746";
+	model = "STMicroelectronics STM32746g-EVAL board";
+	compatible = "st,stm32746g-eval", "st,stm32f746";
 
 	chosen {
-		bootargs = "root=/dev/mmcblk0p1 rw rootwait";
+		bootargs = "root=/dev/ram";
 		stdout-path = "serial0:115200n8";
 	};
 
 	memory {
-		reg = <0xC0000000 0x2000000>;
+		reg = <0xc0000000 0x2000000>;
 	};
 
 	aliases {
 		serial0 = &usart1;
-		spi0 = &qspi;
-		mmc0 = &sdio;
-		/* Aliases for gpios so as to use sequence */
-		gpio0 = &gpioa;
-		gpio1 = &gpiob;
-		gpio2 = &gpioc;
-		gpio3 = &gpiod;
-		gpio4 = &gpioe;
-		gpio5 = &gpiof;
-		gpio6 = &gpiog;
-		gpio7 = &gpioh;
-		gpio8 = &gpioi;
-		gpio9 = &gpioj;
-		gpio10 = &gpiok;
 	};
 
-	led1 {
-		compatible = "st,led1";
-		led-gpio = <&gpiof 10 0>;
+	leds {
+		compatible = "gpio-leds";
+		green {
+			gpios = <&gpiof 10 1>;
+			linux,default-trigger = "heartbeat";
+		};
+		red {
+			gpios = <&gpiob 7 1>;
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+		button@0 {
+			label = "Wake up";
+			linux,code = <KEY_WAKEUP>;
+			gpios = <&gpioc 13 0>;
+		};
+	};
+
+	usbotg_hs_phy: usb-phy {
+		#phy-cells = <0>;
+		compatible = "usb-nop-xceiv";
+		clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
+		clock-names = "main_clk";
 	};
 
-	button1 {
-		compatible = "st,button1";
-		button-gpio = <&gpioc 13 0>;
+	mmc_vcard: mmc_vcard {
+		compatible = "regulator-fixed";
+		regulator-name = "mmc_vcard";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
 	};
 };
 
@@ -94,147 +104,43 @@
 	clock-frequency = <25000000>;
 };
 
-&pinctrl {
-	usart1_pins_a: usart1@0	{
-		pins1 {
-		       pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
-				bias-disable;
-				drive-push-pull;
-				slew-rate = <2>;
-		};
-		pins2 {
-			pinmux = <STM32F746_PA10_FUNC_USART1_RX>;
-			bias-disable;
-		};
-	};
-
-	ethernet_mii: mii@0 {
-	      pins {
-		      pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
-			     <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
-			     <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
-			     <STM32F746_PA2_FUNC_ETH_MDIO>,
-			     <STM32F746_PC1_FUNC_ETH_MDC>,
-			     <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
-			     <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
-			     <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
-			     <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
-		      slew-rate = <2>;
-	      };
-	};
-
-	fmc_pins: fmc@0 {
-		pins {
-			pinmux = <STM32F746_PI10_FUNC_FMC_D31>, /* FMC_D31 */
-				 <STM32F746_PI9_FUNC_FMC_D30>,  /* FMC_D30*/
-				 <STM32F746_PI7_FUNC_FMC_D29>,  /* FMC_D29 */
-				 <STM32F746_PI6_FUNC_FMC_D28>,  /* FMC_D28 */
-				 <STM32F746_PI3_FUNC_FMC_D27>,  /* FMC_D27 */
-				 <STM32F746_PI2_FUNC_FMC_D26>,  /* FMC_D26 */
-				 <STM32F746_PI1_FUNC_FMC_D25>,  /* FMC_D25 */
-				 <STM32F746_PI0_FUNC_FMC_D24>,  /* FMC_D24 */
-				 <STM32F746_PH15_FUNC_FMC_D23>, /* FMC_D23 */
-				 <STM32F746_PH14_FUNC_FMC_D22>, /* FMC_D22 */
-				 <STM32F746_PH13_FUNC_FMC_D21>, /* FMC_D21 */
-				 <STM32F746_PH12_FUNC_FMC_D20>, /* FMC_D20 */
-				 <STM32F746_PH11_FUNC_FMC_D19>, /* FMC_D19 */
-				 <STM32F746_PH10_FUNC_FMC_D18>, /* FMC_D18 */
-				 <STM32F746_PH9_FUNC_FMC_D17>,  /* FMC_D17 */
-				 <STM32F746_PH8_FUNC_FMC_D16>,  /* FMC_D16 */
-
-				 <STM32F746_PD10_FUNC_FMC_D15>, /* FMC_D15 */
-				 <STM32F746_PD9_FUNC_FMC_D14>, /* FMC_D14*/
-				 <STM32F746_PD8_FUNC_FMC_D13>, /* FMC_D13 */
-				 <STM32F746_PE15_FUNC_FMC_D12>,/* FMC_D12 */
-				 <STM32F746_PE14_FUNC_FMC_D11>,/* FMC_D11 */
-				 <STM32F746_PE13_FUNC_FMC_D10>,/* FMC_D10 */
-				 <STM32F746_PE12_FUNC_FMC_D9>, /* FMC_D9 */
-				 <STM32F746_PE11_FUNC_FMC_D8>, /* FMC_D8 */
-				 <STM32F746_PE10_FUNC_FMC_D7>, /* FMC_D7 */
-				 <STM32F746_PE9_FUNC_FMC_D6>,  /* FMC_D6 */
-				 <STM32F746_PE8_FUNC_FMC_D5>,  /* FMC_D5*/
-				 <STM32F746_PE7_FUNC_FMC_D4>,  /* FMC_D4 */
-				 <STM32F746_PD1_FUNC_FMC_D3>,  /* FMC_D3 */
-				 <STM32F746_PD0_FUNC_FMC_D2>,  /* FMC_D2 */
-				 <STM32F746_PD15_FUNC_FMC_D1>, /* FMC_D1 */
-				 <STM32F746_PD14_FUNC_FMC_D0>, /* FMC_D0 */
-
-				 <STM32F746_PI5_FUNC_FMC_NBL3>, /* FMC_NBL3 */
-				 <STM32F746_PI4_FUNC_FMC_NBL2>, /* FMC_NBL2 */
-				 <STM32F746_PE1_FUNC_FMC_NBL1>, /* FMC_NBL1 */
-				 <STM32F746_PE0_FUNC_FMC_NBL0>, /* FMC_NBL0 */
-
-				 <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, /* FMC_A15 FMC_BA1 */
-				 <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, /* FMC_A14 FMC_BA0*/
-
-				 <STM32F746_PG1_FUNC_FMC_A11>, /* FMC_A11 */
-				 <STM32F746_PG0_FUNC_FMC_A10>, /* FMC_A10 */
-				 <STM32F746_PF15_FUNC_FMC_A9>, /* FMC_A9 */
-				 <STM32F746_PF14_FUNC_FMC_A8>, /* FMC_A8 */
-				 <STM32F746_PF13_FUNC_FMC_A7>, /* FMC_A7 */
-				 <STM32F746_PF12_FUNC_FMC_A6>, /* FMC_A6 */
-				 <STM32F746_PF5_FUNC_FMC_A5>,  /* FUNC_FMC_A5 */
-				 <STM32F746_PF4_FUNC_FMC_A4>,  /* FMC_A4 */
-				 <STM32F746_PF3_FUNC_FMC_A3>,  /* FMC_A3 */
-				 <STM32F746_PF2_FUNC_FMC_A2>,  /* FMC_A2 */
-				 <STM32F746_PF1_FUNC_FMC_A1>,  /* FMC_A1 */
-				 <STM32F746_PF0_FUNC_FMC_A0>,  /* FMC_A0 */
-
-				 <STM32F746_PH3_FUNC_FMC_SDNE0>,/* FMC_SDNE0 */
-				 <STM32F746_PH5_FUNC_FMC_SDNWE>, /* FMC_SDNWE */
-				 <STM32F746_PF11_FUNC_FMC_SDNRAS>, /* FMC_SDNRAS */
-				 <STM32F746_PG15_FUNC_FMC_SDNCAS>, /* FMC_SDNCAS */
-				 <STM32F746_PH2_FUNC_FMC_SDCKE0>, /* FMC_SDCKE0 */
-				 <STM32F746_PG8_FUNC_FMC_SDCLK>; /* FMC_SDCLK */
-			  slew-rate = <2>;
-		};
-	};
+&crc {
+	status = "okay";
 };
 
-&usart1 {
-	pinctrl-0 = <&usart1_pins_a>;
+&i2c1 {
+	pinctrl-0 = <&i2c1_pins_b>;
 	pinctrl-names = "default";
+	i2c-scl-rising-time-ns = <185>;
+	i2c-scl-falling-time-ns = <20>;
 	status = "okay";
 };
 
-&mac {
+&rtc {
 	status = "okay";
-	pinctrl-0 = <&ethernet_mii>;
-	phy-mode = "rmii";
-	phy-handle = <&phy0>;
+};
 
-	mdio0 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "snps,dwmac-mdio";
-		phy0: ethernet-phy@0 {
-			reg = <0>;
-		};
-	};
+&sdio1 {
+	status = "okay";
+	vmmc-supply = <&mmc_vcard>;
+	broken-cd;
+	pinctrl-names = "default", "opendrain";
+	pinctrl-0 = <&sdio_pins_a>;
+	pinctrl-1 = <&sdio_pins_od_a>;
+	bus-width = <4>;
 };
 
-&fmc {
-	pinctrl-0 = <&fmc_pins>;
+&usart1 {
+	pinctrl-0 = <&usart1_pins_a>;
 	pinctrl-names = "default";
 	status = "okay";
-
-	/*
-	 * Memory configuration from sdram datasheet IS42S32800G-6BLI
-	 */
-	bank1: bank@0 {
-		st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
-				  CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
-		st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
-				  TWR_1 TRCD_1>;
-		st,sdram-refcount = <1539>;
-	};
 };
 
-&sdio {
+&usbotg_hs {
+	dr_mode = "otg";
+	phys = <&usbotg_hs_phy>;
+	phy-names = "usb2-phy";
+	pinctrl-0 = <&usbotg_hs_pins_a>;
+	pinctrl-names = "default";
 	status = "okay";
-	pinctrl-names = "default", "opendrain";
-	pinctrl-0 = <&sdio_pins>;
-	pinctrl-1 = <&sdio_pins_od>;
-	bus-width = <4>;
-	max-frequency = <25000000>;
 };
diff --git a/arch/arm/dts/stm32f4-pinctrl.dtsi b/arch/arm/dts/stm32f4-pinctrl.dtsi
index 736bca738d3..35202896c09 100644
--- a/arch/arm/dts/stm32f4-pinctrl.dtsi
+++ b/arch/arm/dts/stm32f4-pinctrl.dtsi
@@ -1,6 +1,5 @@
 /*
- * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
- * Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -342,12 +341,12 @@
 
 			sdio_pins: sdio_pins@0 {
 				pins {
-					pinmux = <STM32_PINMUX('C', 8, AF12)>,
-						 <STM32_PINMUX('C', 9, AF12)>,
-						 <STM32_PINMUX('C', 10, AF12)>,
-						 <STM32_PINMUX('c', 11, AF12)>,
-						 <STM32_PINMUX('C', 12, AF12)>,
-						 <STM32_PINMUX('D', 2, AF12)>;
+					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
+						 <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
+						 <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
+						 <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
+						 <STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */
+						 <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
 					drive-push-pull;
 					slew-rate = <2>;
 				};
@@ -355,17 +354,17 @@
 
 			sdio_pins_od: sdio_pins_od@0 {
 				pins1 {
-					pinmux = <STM32_PINMUX('C', 8, AF12)>,
-						 <STM32_PINMUX('C', 9, AF12)>,
-						 <STM32_PINMUX('C', 10, AF12)>,
-						 <STM32_PINMUX('C', 11, AF12)>,
-						 <STM32_PINMUX('C', 12, AF12)>;
+					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
+						 <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
+						 <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
+						 <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
+						 <STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */
 					drive-push-pull;
 					slew-rate = <2>;
 				};
 
 				pins2 {
-					pinmux = <STM32_PINMUX('D', 2, AF12)>;
+					pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
 					drive-open-drain;
 					slew-rate = <2>;
 				};
diff --git a/arch/arm/dts/stm32f429-disco-u-boot.dtsi b/arch/arm/dts/stm32f429-disco-u-boot.dtsi
index 10e09508aa2..0cc3100440c 100644
--- a/arch/arm/dts/stm32f429-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f429-disco-u-boot.dtsi
@@ -70,19 +70,11 @@
 	u-boot,dm-pre-reloc;
 };
 
-&clk_lse {
-	u-boot,dm-pre-reloc;
-};
-
 &clk_i2s_ckin {
 	u-boot,dm-pre-reloc;
 };
 
-&pwrcfg {
-	u-boot,dm-pre-reloc;
-};
-
-&rcc {
+&clk_lse {
 	u-boot,dm-pre-reloc;
 };
 
@@ -203,3 +195,11 @@
 		};
 	};
 };
+
+&pwrcfg {
+	u-boot,dm-pre-reloc;
+};
+
+&rcc {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/stm32f429-disco.dts b/arch/arm/dts/stm32f429-disco.dts
index 106db68b5b9..d99f47aa724 100644
--- a/arch/arm/dts/stm32f429-disco.dts
+++ b/arch/arm/dts/stm32f429-disco.dts
@@ -1,6 +1,5 @@
 /*
- * Copyright (C) 2015, STMicroelectronics - All Rights Reserved
- * Author(s):  Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
+ * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -76,6 +75,7 @@
 
 	gpio_keys {
 		compatible = "gpio-keys";
+		#address-cells = <1>;
 		#size-cells = <0>;
 		autorepeat;
 		button@0 {
diff --git a/arch/arm/dts/stm32f429-pinctrl.dtsi b/arch/arm/dts/stm32f429-pinctrl.dtsi
index 77246b3d79e..3e7a17d9112 100644
--- a/arch/arm/dts/stm32f429-pinctrl.dtsi
+++ b/arch/arm/dts/stm32f429-pinctrl.dtsi
@@ -1,6 +1,5 @@
 /*
- * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
- * Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
diff --git a/arch/arm/dts/stm32f429.dtsi b/arch/arm/dts/stm32f429.dtsi
index 046aeff7ccc..c5c029b9e36 100644
--- a/arch/arm/dts/stm32f429.dtsi
+++ b/arch/arm/dts/stm32f429.dtsi
@@ -1,6 +1,5 @@
 /*
- * Copyright (C) 2015, STMicroelectronics - All Rights Reserved
- * Author(s):  Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
+ * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -259,6 +258,7 @@
 		};
 
 		timers13: timers@40001c00 {
+			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "st,stm32-timers";
 			reg = <0x40001C00 0x400>;
@@ -273,6 +273,7 @@
 		};
 
 		timers14: timers@40002000 {
+			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "st,stm32-timers";
 			reg = <0x40002000 0x400>;
@@ -296,7 +297,7 @@
 			interrupt-parent = <&exti>;
 			interrupts = <17 1>;
 			interrupt-names = "alarm";
-			st,syscfg = <&pwrcfg>;
+			st,syscfg = <&pwrcfg 0x00 0x100>;
 			status = "disabled";
 		};
 
@@ -304,6 +305,7 @@
 			compatible = "st,stm32-iwdg";
 			reg = <0x40003000 0x400>;
 			clocks = <&clk_lsi>;
+			clock-names = "lsi";
 			status = "disabled";
 		};
 
@@ -505,6 +507,17 @@
 			};
 		};
 
+		sdio: sdio@40012c00 {
+			compatible = "arm,pl180", "arm,primecell";
+			arm,primecell-periphid = <0x00880180>;
+			reg = <0x40012c00 0x400>;
+			clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
+			clock-names = "apb_pclk";
+			interrupts = <49>;
+			max-frequency = <48000000>;
+			status = "disabled";
+		};
+
 		syscfg: system-config@40013800 {
 			compatible = "syscon";
 			reg = <0x40013800 0x400>;
@@ -540,6 +553,7 @@
 		};
 
 		timers10: timers@40014400 {
+			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "st,stm32-timers";
 			reg = <0x40014400 0x400>;
@@ -554,6 +568,7 @@
 		};
 
 		timers11: timers@40014800 {
+			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "st,stm32-timers";
 			reg = <0x40014800 0x400>;
@@ -572,18 +587,6 @@
 			reg = <0x40007000 0x400>;
 		};
 
-		sdio: sdio@40012c00 {
-			compatible = "st,stm32f4xx-sdio";
-			reg = <0x40012c00 0x400>;
-			clocks = <&rcc 0 171>;
-			interrupts = <49>;
-			status = "disabled";
-			pinctrl-0 = <&sdio_pins>;
-			pinctrl-1 = <&sdio_pins_od>;
-			pinctrl-names = "default", "opendrain";
-			max-frequency = <48000000>;
-		};
-
 		ltdc: display-controller@40016800 {
 			compatible = "st,stm32-ltdc";
 			reg = <0x40016800 0x200>;
diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi b/arch/arm/dts/stm32f469-disco-u-boot.dtsi
index 774f1b5e656..a980ac46f56 100644
--- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi
@@ -71,23 +71,11 @@
 	u-boot,dm-pre-reloc;
 };
 
-&clk_lse {
-	u-boot,dm-pre-reloc;
-};
-
 &clk_i2s_ckin {
 	u-boot,dm-pre-reloc;
 };
 
-&pwrcfg {
-	u-boot,dm-pre-reloc;
-};
-
-&syscfg {
-	u-boot,dm-pre-reloc;
-};
-
-&rcc {
+&clk_lse {
 	u-boot,dm-pre-reloc;
 };
 
@@ -147,16 +135,6 @@
 };
 
 &pinctrl {
-	usart3_pins_a: usart3@0	{
-		u-boot,dm-pre-reloc;
-		pins1 {
-			u-boot,dm-pre-reloc;
-		};
-		pins2 {
-			u-boot,dm-pre-reloc;
-		};
-	};
-
 	fmc_pins_d32: fmc_d32@0 {
 		u-boot,dm-pre-reloc;
 		pins
@@ -226,4 +204,26 @@
 			u-boot,dm-pre-reloc;
 		};
 	};
+
+	usart3_pins_a: usart3@0	{
+		u-boot,dm-pre-reloc;
+		pins1 {
+			u-boot,dm-pre-reloc;
+		};
+		pins2 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
+
+&pwrcfg {
+	u-boot,dm-pre-reloc;
+};
+
+&rcc {
+	u-boot,dm-pre-reloc;
+};
+
+&syscfg {
+	u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/stm32f469-disco.dts b/arch/arm/dts/stm32f469-disco.dts
index 3ecef286736..3ceb84d8ba8 100644
--- a/arch/arm/dts/stm32f469-disco.dts
+++ b/arch/arm/dts/stm32f469-disco.dts
@@ -41,8 +41,10 @@
  */
 
 /dts-v1/;
-#include "stm32f429.dtsi"
+#include "stm32f469.dtsi"
 #include "stm32f469-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 
 / {
 	model = "STMicroelectronics STM32F469i-DISCO board";
@@ -72,11 +74,40 @@
 		dma-ranges = <0xc0000000 0x0 0x10000000>;
 	};
 
+	leds {
+		compatible = "gpio-leds";
+		green {
+			gpios = <&gpiog 6 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "heartbeat";
+		};
+		orange {
+			gpios = <&gpiod 4 GPIO_ACTIVE_LOW>;
+		};
+		red {
+			gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
+		};
+		blue {
+			gpios = <&gpiok 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+		button@0 {
+			label = "User";
+			linux,code = <KEY_WAKEUP>;
+			gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
 	/* This turns on vbus for otg for host mode (dwc2) */
 	vcc5v_otg: vcc5v-otg-regulator {
 		compatible = "regulator-fixed";
 		enable-active-high;
-		gpio = <&gpiob 2 0>;
+		gpio = <&gpiob 2 GPIO_ACTIVE_HIGH>;
 		regulator-name = "vcc5_host1";
 		regulator-always-on;
 	};
@@ -90,6 +121,55 @@
 	clock-frequency = <8000000>;
 };
 
+&dsi {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			dsi_in: endpoint {
+				remote-endpoint = <&ltdc_out_dsi>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			dsi_out: endpoint {
+				remote-endpoint = <&dsi_panel_in>;
+			};
+		};
+	};
+
+	panel-dsi@0 {
+		compatible = "orisetech,otm8009a";
+		reg = <0>; /* dsi virtual channel (0..3) */
+		reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
+		status = "okay";
+
+		port {
+			dsi_panel_in: endpoint {
+				remote-endpoint = <&dsi_out>;
+			};
+		};
+	};
+};
+
+&ltdc {
+	dma-ranges;
+	status = "okay";
+
+	port {
+		ltdc_out_dsi: endpoint@0 {
+			remote-endpoint = <&dsi_in>;
+		};
+	};
+};
+
 &rtc {
 	status = "okay";
 };
@@ -125,6 +205,8 @@
 &sdio {
 	status = "okay";
 	vmmc-supply = <&mmc_vcard>;
+	cd-gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
+	broken-cd;
 	pinctrl-names = "default", "opendrain";
 	pinctrl-0 = <&sdio_pins>;
 	pinctrl-1 = <&sdio_pins_od>;
diff --git a/arch/arm/dts/stm32f469-pinctrl.dtsi b/arch/arm/dts/stm32f469-pinctrl.dtsi
index dd641580c9b..fff542662ee 100644
--- a/arch/arm/dts/stm32f469-pinctrl.dtsi
+++ b/arch/arm/dts/stm32f469-pinctrl.dtsi
@@ -1,6 +1,5 @@
 /*
- * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
- * Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
diff --git a/arch/arm/dts/stm32f469.dtsi b/arch/arm/dts/stm32f469.dtsi
new file mode 100644
index 00000000000..0d58d40649f
--- /dev/null
+++ b/arch/arm/dts/stm32f469.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (C) STMicroelectronics 2017 - All Rights Reserved */
+
+#include "stm32f429.dtsi"
+
+/ {
+	soc {
+		dsi: dsi@40016c00 {
+			compatible = "st,stm32-dsi";
+			reg = <0x40016c00 0x800>;
+			interrupts = <92>;
+			resets = <&rcc STM32F4_APB2_RESET(DSI)>;
+			reset-names = "apb";
+			clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
+			clock-names = "pclk", "ref";
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/dts/stm32f7-pinctrl.dtsi b/arch/arm/dts/stm32f7-pinctrl.dtsi
new file mode 100644
index 00000000000..9314128df18
--- /dev/null
+++ b/arch/arm/dts/stm32f7-pinctrl.dtsi
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Alexandre Torgue  <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+#include <dt-bindings/mfd/stm32f7-rcc.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x40020000 0x3000>;
+			interrupt-parent = <&exti>;
+			st,syscfg = <&syscfg 0x8>;
+			pins-are-numbered;
+
+			gpioa: gpio@40020000 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0x0 0x400>;
+				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
+				st,bank-name = "GPIOA";
+			};
+
+			gpiob: gpio@40020400 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0x400 0x400>;
+				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
+				st,bank-name = "GPIOB";
+			};
+
+			gpioc: gpio@40020800 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0x800 0x400>;
+				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
+				st,bank-name = "GPIOC";
+			};
+
+			gpiod: gpio@40020c00 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0xc00 0x400>;
+				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
+				st,bank-name = "GPIOD";
+			};
+
+			gpioe: gpio@40021000 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0x1000 0x400>;
+				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
+				st,bank-name = "GPIOE";
+			};
+
+			gpiof: gpio@40021400 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0x1400 0x400>;
+				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
+				st,bank-name = "GPIOF";
+			};
+
+			gpiog: gpio@40021800 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0x1800 0x400>;
+				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
+				st,bank-name = "GPIOG";
+			};
+
+			gpioh: gpio@40021c00 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0x1c00 0x400>;
+				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
+				st,bank-name = "GPIOH";
+			};
+
+			gpioi: gpio@40022000 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0x2000 0x400>;
+				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
+				st,bank-name = "GPIOI";
+			};
+
+			gpioj: gpio@40022400 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0x2400 0x400>;
+				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
+				st,bank-name = "GPIOJ";
+			};
+
+			gpiok: gpio@40022800 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0x2800 0x400>;
+				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
+				st,bank-name = "GPIOK";
+			};
+
+			cec_pins_a: cec@0 {
+				pins {
+					pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
+					slew-rate = <0>;
+					drive-open-drain;
+					bias-disable;
+				};
+			};
+
+			usart1_pins_a: usart1@0 {
+				pins1 {
+					pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <0>;
+				};
+				pins2 {
+					pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
+					bias-disable;
+				};
+			};
+
+			usart1_pins_b: usart1@1 {
+				pins1 {
+					pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <0>;
+				};
+				pins2 {
+					pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
+					bias-disable;
+				};
+			};
+
+			i2c1_pins_b: i2c1@0 {
+				pins {
+					pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
+						 <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
+					bias-disable;
+					drive-open-drain;
+					slew-rate = <0>;
+				};
+			};
+
+			usbotg_hs_pins_a: usbotg-hs@0 {
+				pins {
+					pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
+						 <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
+						 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
+						 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
+						 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
+						 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
+						 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
+						 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
+						 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
+						 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
+						 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
+						 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+			};
+
+			usbotg_hs_pins_b: usbotg-hs@1 {
+				pins {
+					pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
+						 <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
+						 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
+						 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
+						 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
+						 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
+						 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
+						 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
+						 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
+						 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
+						 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
+						 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+			};
+
+			usbotg_fs_pins_a: usbotg-fs@0 {
+				pins {
+					pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
+						 <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
+						 <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+			};
+
+			sdio_pins_a: sdio_pins_a@0 {
+				pins {
+					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
+						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
+						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
+						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
+						 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
+						 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+			};
+
+			sdio_pins_od_a: sdio_pins_od_a@0 {
+				pins1 {
+					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
+						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
+						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
+						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
+						 <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+
+				pins2 {
+					pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
+					drive-open-drain;
+					slew-rate = <2>;
+				};
+			};
+
+			sdio_pins_b: sdio_pins_b@0 {
+				pins {
+					pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
+						 <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
+						 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
+						 <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
+						 <STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
+						 <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+			};
+
+			sdio_pins_od_b: sdio_pins_od_b@0 {
+				pins1 {
+					pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
+						 <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
+						 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
+						 <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
+						 <STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+
+				pins2 {
+					pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
+					drive-open-drain;
+					slew-rate = <2>;
+				};
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi
index 4a677192a2d..29b157324e6 100644
--- a/arch/arm/dts/stm32f7-u-boot.dtsi
+++ b/arch/arm/dts/stm32f7-u-boot.dtsi
@@ -1,21 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <dt-bindings/memory/stm32-sdram.h>
 /{
 	soc {
-		timer5: timer@40000c00 {
+		u-boot,dm-pre-reloc;
+
+		fmc: fmc@A0000000 {
+			compatible = "st,stm32-fmc";
+			reg = <0xA0000000 0x1000>;
+			clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
+			pinctrl-0 = <&fmc_pins>;
+			pinctrl-names = "default";
+			status = "okay";
 			u-boot,dm-pre-reloc;
 		};
-	};
-};
 
-&pinctrl {
-	usart1_pins_a: usart1@0	{
-		u-boot,dm-pre-reloc;
-		pins1 {
-			u-boot,dm-pre-reloc;
+		mac: ethernet@40028000 {
+			compatible = "st,stm32-dwmac";
+			reg = <0x40028000 0x8000>;
+			reg-names = "stmmaceth";
+			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
+				 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
+				 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
+			interrupts = <61>, <62>;
+			interrupt-names = "macirq", "eth_wake_irq";
+			snps,pbl = <8>;
+			snps,mixed-burst;
+			dma-ranges;
+			pinctrl-0 = <&ethernet_mii>;
+			phy-mode = "rmii";
+			phy-handle = <&phy0>;
+
+			status = "okay";
+
+			mdio0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,dwmac-mdio";
+				phy0: ethernet-phy@0 {
+					reg = <0>;
+				};
+			};
 		};
-		pins2 {
-			u-boot,dm-pre-reloc;
+
+		qspi: quadspi@A0001000 {
+			compatible = "st,stm32-qspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
+			reg-names = "qspi", "qspi_mm";
+			interrupts = <92>;
+			spi-max-frequency = <108000000>;
+			clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
+			resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
+			pinctrl-0 = <&qspi_pins>;
+
+			status = "okay";
 		};
 	};
+};
+
+&clk_hse {
+	u-boot,dm-pre-reloc;
+};
+
+&gpioa {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpiob {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpioc {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpiod {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpioe {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpiof {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpiog {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpioh {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpioi {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpioj {
+	compatible = "st,stm32-gpio";
+};
+
+&gpiok {
+	compatible = "st,stm32-gpio";
+};
+
+&pinctrl {
+	u-boot,dm-pre-reloc;
+
 	fmc_pins: fmc@0 {
 		u-boot,dm-pre-reloc;
 		pins
@@ -25,16 +129,19 @@
 	};
 };
 
-&fmc {
-	bank1: bank@0 {
-		 u-boot,dm-pre-reloc;
-	};
+&pwrcfg {
+	u-boot,dm-pre-reloc;
 };
 
-&pwrcfg {
+&rcc {
 	u-boot,dm-pre-reloc;
 };
 
-&clk_hse {
+&timer5 {
+	u-boot,dm-pre-reloc;
+};
+
+&usart1 {
 	u-boot,dm-pre-reloc;
+	clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
 };
diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
new file mode 100644
index 00000000000..bc337b1628b
--- /dev/null
+++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <stm32f7-u-boot.dtsi>
+/{
+	chosen {
+		bootargs = "root=/dev/ram rdinit=/linuxrc";
+	};
+
+	aliases {
+		/* Aliases for gpios so as to use sequence */
+		gpio0 = &gpioa;
+		gpio1 = &gpiob;
+		gpio2 = &gpioc;
+		gpio3 = &gpiod;
+		gpio4 = &gpioe;
+		gpio5 = &gpiof;
+		gpio6 = &gpiog;
+		gpio7 = &gpioh;
+		gpio8 = &gpioi;
+		gpio9 = &gpioj;
+		gpio10 = &gpiok;
+		mmc0 = &sdio1;
+		spi0 = &qspi;
+	};
+
+	backlight: backlight {
+		compatible = "gpio-backlight";
+		gpios = <&gpiok 3 0>;
+		status = "okay";
+	};
+
+	button1 {
+		compatible = "st,button1";
+		button-gpio = <&gpioi 11 0>;
+	};
+
+	led1 {
+		compatible = "st,led1";
+		led-gpio = <&gpioi 1 0>;
+	};
+
+	panel-rgb@0 {
+		compatible = "simple-panel";
+		backlight = <&backlight>;
+		enable-gpios = <&gpioi 12 0>;
+		status = "okay";
+
+		display-timings {
+			timing@0 {
+				clock-frequency = <9000000>;
+				hactive = <480>;
+				vactive = <272>;
+				hfront-porch = <2>;
+				hback-porch = <2>;
+				hsync-len = <41>;
+				vfront-porch = <2>;
+				vback-porch = <2>;
+				vsync-len = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <0>;
+				pixelclk-active = <1>;
+			};
+		};
+	};
+
+	soc {
+		ltdc: display-controller@40016800 {
+			compatible = "st,stm32-ltdc";
+			reg = <0x40016800 0x200>;
+			resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
+			clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
+			pinctrl-0 = <&ltdc_pins>;
+
+			status = "okay";
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
+
+&clk_hse {
+	u-boot,dm-pre-reloc;
+};
+
+&fmc {
+	/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
+	bank1: bank@0 {
+		u-boot,dm-pre-reloc;
+		st,sdram-control = /bits/ 8 <NO_COL_8
+					     NO_ROW_12
+					     MWIDTH_16
+					     BANKS_4
+					     CAS_3
+					     SDCLK_2
+					     RD_BURST_EN
+					     RD_PIPE_DL_0>;
+		st,sdram-timing = /bits/ 8 <TMRD_2
+					    TXSR_6
+					    TRAS_4
+					    TRC_6
+					    TWR_2
+					    TRP_2
+					    TRCD_2>;
+		/* refcount = (64msec/total_row_sdram)*freq - 20 */
+		st,sdram-refcount = < 1542 >;
+	};
+};
+
+&pinctrl {
+	ethernet_mii: mii@0 {
+		pins {
+			pinmux = <STM32_PINMUX('G',13, AF11)>, /* ETH_RMII_TXD0 */
+				 <STM32_PINMUX('G',14, AF11)>, /* ETH_RMII_TXD1 */
+				 <STM32_PINMUX('G',11, AF11)>, /* ETH_RMII_TX_EN */
+				 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
+				 <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
+				 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
+				 <STM32_PINMUX('A', 7, AF11)>, /* ETH_RMII_CRS_DV */
+				 <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
+				 <STM32_PINMUX('C', 5, AF11)>; /* ETH_RMII_RXD1 */
+			slew-rate = <2>;
+		};
+	};
+
+	fmc_pins: fmc@0 {
+		u-boot,dm-pre-reloc;
+		pins {
+			u-boot,dm-pre-reloc;
+			pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
+				 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
+				 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
+				 <STM32_PINMUX('E',15, AF12)>, /* D12 */
+				 <STM32_PINMUX('E',14, AF12)>, /* D11 */
+				 <STM32_PINMUX('E',13, AF12)>, /* D10 */
+				 <STM32_PINMUX('E',12, AF12)>, /* D9 */
+				 <STM32_PINMUX('E',11, AF12)>, /* D8 */
+				 <STM32_PINMUX('E',10, AF12)>, /* D7 */
+				 <STM32_PINMUX('E', 9, AF12)>, /* D6 */
+				 <STM32_PINMUX('E', 8, AF12)>, /* D5 */
+				 <STM32_PINMUX('E', 7, AF12)>, /* D4 */
+				 <STM32_PINMUX('D', 1, AF12)>, /* D3 */
+				 <STM32_PINMUX('D', 0, AF12)>, /* D2 */
+				 <STM32_PINMUX('D',15, AF12)>, /* D1 */
+				 <STM32_PINMUX('D',14, AF12)>, /* D0 */
+
+				 <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
+				 <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
+
+				 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
+				 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
+
+				 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
+				 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
+				 <STM32_PINMUX('F',15, AF12)>, /* A9 */
+				 <STM32_PINMUX('F',14, AF12)>, /* A8 */
+				 <STM32_PINMUX('F',13, AF12)>, /* A7 */
+				 <STM32_PINMUX('F',12, AF12)>, /* A6 */
+				 <STM32_PINMUX('F', 5, AF12)>, /* A5 */
+				 <STM32_PINMUX('F', 4, AF12)>, /* A4 */
+				 <STM32_PINMUX('F', 3, AF12)>, /* A3 */
+				 <STM32_PINMUX('F', 2, AF12)>, /* A2 */
+				 <STM32_PINMUX('F', 1, AF12)>, /* A1 */
+				 <STM32_PINMUX('F', 0, AF12)>, /* A0 */
+
+				 <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
+				 <STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
+				 <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
+				 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
+				 <STM32_PINMUX('C', 3, AF12)>, /* SDCKE0 */
+				 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
+			slew-rate = <2>;
+		};
+	};
+
+	ltdc_pins: ltdc@0 {
+		pins {
+			pinmux = <STM32_PINMUX('E', 4, AF14)>, /* B0 */
+				 <STM32_PINMUX('G',12, AF14)>, /* B4 */
+				 <STM32_PINMUX('I', 9, AF14)>, /* VSYNC */
+				 <STM32_PINMUX('I',10, AF14)>, /* HSYNC */
+				 <STM32_PINMUX('I',14, AF14)>, /* CLK */
+				 <STM32_PINMUX('I',15, AF14)>, /* R0 */
+				 <STM32_PINMUX('J', 0, AF14)>, /* R1 */
+				 <STM32_PINMUX('J', 1, AF14)>, /* R2 */
+				 <STM32_PINMUX('J', 2, AF14)>, /* R3 */
+				 <STM32_PINMUX('J', 3, AF14)>, /* R4 */
+				 <STM32_PINMUX('J', 4, AF14)>, /* R5 */
+				 <STM32_PINMUX('J', 5, AF14)>, /* R6 */
+				 <STM32_PINMUX('J', 6, AF14)>, /* R7 */
+				 <STM32_PINMUX('J', 7, AF14)>, /* G0 */
+				 <STM32_PINMUX('J', 8, AF14)>, /* G1 */
+				 <STM32_PINMUX('J', 9, AF14)>, /* G2 */
+				 <STM32_PINMUX('J',10, AF14)>, /* G3 */
+				 <STM32_PINMUX('J',11, AF14)>, /* G4 */
+				 <STM32_PINMUX('J',13, AF14)>, /* B1 */
+				 <STM32_PINMUX('J',14, AF14)>, /* B2 */
+				 <STM32_PINMUX('J',15, AF14)>, /* B3 */
+				 <STM32_PINMUX('K', 0, AF14)>, /* G5 */
+				 <STM32_PINMUX('K', 1, AF14)>, /* G6 */
+				 <STM32_PINMUX('K', 2, AF14)>, /* G7 */
+				 <STM32_PINMUX('K', 4, AF14)>, /* B5 */
+				 <STM32_PINMUX('K', 5, AF14)>, /* B6 */
+				 <STM32_PINMUX('K', 6, AF14)>, /* B7 */
+				 <STM32_PINMUX('K', 7, AF14)>; /* DE */
+			slew-rate = <2>;
+		};
+	};
+
+	qspi_pins: qspi@0 {
+		pins {
+			pinmux = <STM32_PINMUX('B', 2, AF9)>, /* CLK */
+				 <STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */
+				 <STM32_PINMUX('D',11, AF9)>, /* BK1_IO0 */
+				 <STM32_PINMUX('D',12, AF9)>, /* BK1_IO1 */
+				 <STM32_PINMUX('D',13, AF9)>, /* BK1_IO3 */
+				 <STM32_PINMUX('E', 2, AF9)>; /* BK1_IO2 */
+			slew-rate = <2>;
+		};
+	};
+
+	usart1_pins_b: usart1@1	{
+		u-boot,dm-pre-reloc;
+		pins1 {
+			u-boot,dm-pre-reloc;
+		};
+		pins2 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
+
+&pwrcfg {
+	u-boot,dm-pre-reloc;
+};
+
+&qspi {
+	qflash0: n25q128a {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q128a13", "jedec,spi-nor";
+		spi-max-frequency = <108000000>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+		memory-map = <0x90000000 0x1000000>;
+		reg = <0>;
+	};
+};
+
+&timer5 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts
index babd37f1c11..e3a7bd338d6 100644
--- a/arch/arm/dts/stm32f746-disco.dts
+++ b/arch/arm/dts/stm32f746-disco.dts
@@ -1,10 +1,5 @@
 /*
- * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
- * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
- *
- * Based on:
- * stm32f469-disco.dts from Linux
- * Copyright 2016 - Lee Jones <lee.jones@linaro.org>
+ * Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -47,7 +42,8 @@
 
 /dts-v1/;
 #include "stm32f746.dtsi"
-#include <dt-bindings/memory/stm32-sdram.h>
+#include "stm32f746-pinctrl.dtsi"
+#include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -55,7 +51,7 @@
 	compatible = "st,stm32f746-disco", "st,stm32f746";
 
 	chosen {
-		bootargs = "root=/dev/ram rdinit=/linuxrc";
+		bootargs = "root=/dev/ram";
 		stdout-path = "serial0:115200n8";
 	};
 
@@ -65,61 +61,28 @@
 
 	aliases {
 		serial0 = &usart1;
-		spi0 = &qspi;
-		mmc0 = &sdio;
-		/* Aliases for gpios so as to use sequence */
-		gpio0 = &gpioa;
-		gpio1 = &gpiob;
-		gpio2 = &gpioc;
-		gpio3 = &gpiod;
-		gpio4 = &gpioe;
-		gpio5 = &gpiof;
-		gpio6 = &gpiog;
-		gpio7 = &gpioh;
-		gpio8 = &gpioi;
-		gpio9 = &gpioj;
-		gpio10 = &gpiok;
 	};
 
-	led1 {
-		compatible = "st,led1";
-		led-gpio = <&gpioi 1 0>;
+	usbotg_hs_phy: usb-phy {
+		#phy-cells = <0>;
+		compatible = "usb-nop-xceiv";
+		clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
+		clock-names = "main_clk";
 	};
 
-	button1 {
-		compatible = "st,button1";
-		button-gpio = <&gpioi 11 0>;
+	/* This turns on vbus for otg fs for host mode (dwc2) */
+	vcc5v_otg_fs: vcc5v-otg-fs-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpiod 5 0>;
+		regulator-name = "vcc5_host1";
+		regulator-always-on;
 	};
 
-	backlight: backlight {
-		compatible = "gpio-backlight";
-		gpios = <&gpiok 3 0>;
-		status = "okay";
-	};
-
-	panel-rgb@0 {
-		compatible = "simple-panel";
-		backlight = <&backlight>;
-		enable-gpios = <&gpioi 12 0>;
-		status = "okay";
-
-		display-timings {
-			timing@0 {
-				clock-frequency = <9000000>;
-				hactive = <480>;
-				vactive = <272>;
-				hfront-porch = <2>;
-				hback-porch = <2>;
-				hsync-len = <41>;
-				vfront-porch = <2>;
-				vback-porch = <2>;
-				vsync-len = <10>;
-				hsync-active = <0>;
-				vsync-active = <0>;
-				de-active = <0>;
-				pixelclk-active = <1>;
-			};
-		};
+	mmc_vcard: mmc_vcard {
+		compatible = "regulator-fixed";
+		regulator-name = "mmc_vcard";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
 	};
 };
 
@@ -127,196 +90,42 @@
 	clock-frequency = <25000000>;
 };
 
-&pinctrl {
-	usart1_pins_a: usart1@0	{
-		pins1 {
-		       pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
-				bias-disable;
-				drive-push-pull;
-				slew-rate = <2>;
-		};
-		pins2 {
-			pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
-			bias-disable;
-		};
-	};
-
-	ethernet_mii: mii@0 {
-	      pins {
-		      pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
-			     <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
-			     <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
-			     <STM32F746_PA2_FUNC_ETH_MDIO>,
-			     <STM32F746_PC1_FUNC_ETH_MDC>,
-			     <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
-			     <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
-			     <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
-			     <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
-		      slew-rate = <2>;
-	      };
-	};
-
-	qspi_pins: qspi@0 {
-		pins {
-			pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
-			       <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
-			       <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
-			       <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
-			       <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
-			       <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
-			slew-rate = <2>;
-		};
-	};
-
-	fmc_pins: fmc@0 {
-		pins {
-			pinmux = <STM32F746_PD10_FUNC_FMC_D15>,
-				 <STM32F746_PD9_FUNC_FMC_D14>,
-				 <STM32F746_PD8_FUNC_FMC_D13>,
-				 <STM32F746_PE15_FUNC_FMC_D12>,
-				 <STM32F746_PE14_FUNC_FMC_D11>,
-				 <STM32F746_PE13_FUNC_FMC_D10>,
-				 <STM32F746_PE12_FUNC_FMC_D9>,
-				 <STM32F746_PE11_FUNC_FMC_D8>,
-				 <STM32F746_PE10_FUNC_FMC_D7>,
-				 <STM32F746_PE9_FUNC_FMC_D6>,
-				 <STM32F746_PE8_FUNC_FMC_D5>,
-				 <STM32F746_PE7_FUNC_FMC_D4>,
-				 <STM32F746_PD1_FUNC_FMC_D3>,
-				 <STM32F746_PD0_FUNC_FMC_D2>,
-				 <STM32F746_PD15_FUNC_FMC_D1>,
-				 <STM32F746_PD14_FUNC_FMC_D0>,
-
-				 <STM32F746_PE1_FUNC_FMC_NBL1>,
-				 <STM32F746_PE0_FUNC_FMC_NBL0>,
-
-				 <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
-				 <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
-
-				 <STM32F746_PG1_FUNC_FMC_A11>,
-				 <STM32F746_PG0_FUNC_FMC_A10>,
-				 <STM32F746_PF15_FUNC_FMC_A9>,
-				 <STM32F746_PF14_FUNC_FMC_A8>,
-				 <STM32F746_PF13_FUNC_FMC_A7>,
-				 <STM32F746_PF12_FUNC_FMC_A6>,
-				 <STM32F746_PF5_FUNC_FMC_A5>,
-				 <STM32F746_PF4_FUNC_FMC_A4>,
-				 <STM32F746_PF3_FUNC_FMC_A3>,
-				 <STM32F746_PF2_FUNC_FMC_A2>,
-				 <STM32F746_PF1_FUNC_FMC_A1>,
-				 <STM32F746_PF0_FUNC_FMC_A0>,
-
-				 <STM32F746_PH3_FUNC_FMC_SDNE0>,
-				 <STM32F746_PH5_FUNC_FMC_SDNWE>,
-				 <STM32F746_PF11_FUNC_FMC_SDNRAS>,
-				 <STM32F746_PG15_FUNC_FMC_SDNCAS>,
-				 <STM32F746_PC3_FUNC_FMC_SDCKE0>,
-				 <STM32F746_PG8_FUNC_FMC_SDCLK>;
-			  slew-rate = <2>;
-		};
-	};
-
-	ltdc_pins: ltdc@0 {
-		pins {
-			pinmux = <STM32F746_PE4_FUNC_LCD_B0>,
-			       <STM32F746_PG12_FUNC_LCD_B4>,
-			       <STM32F746_PI9_FUNC_LCD_VSYNC>,
-			       <STM32F746_PI10_FUNC_LCD_HSYNC>,
-			       <STM32F746_PI14_FUNC_LCD_CLK>,
-			       <STM32F746_PI15_FUNC_LCD_R0>,
-			       <STM32F746_PJ0_FUNC_LCD_R1>,
-			       <STM32F746_PJ1_FUNC_LCD_R2>,
-			       <STM32F746_PJ2_FUNC_LCD_R3>,
-			       <STM32F746_PJ3_FUNC_LCD_R4>,
-			       <STM32F746_PJ4_FUNC_LCD_R5>,
-			       <STM32F746_PJ5_FUNC_LCD_R6>,
-			       <STM32F746_PJ6_FUNC_LCD_R7>,
-			       <STM32F746_PJ7_FUNC_LCD_G0>,
-			       <STM32F746_PJ8_FUNC_LCD_G1>,
-			       <STM32F746_PJ9_FUNC_LCD_G2>,
-			       <STM32F746_PJ10_FUNC_LCD_G3>,
-			       <STM32F746_PJ11_FUNC_LCD_G4>,
-			       <STM32F746_PJ13_FUNC_LCD_B1>,
-			       <STM32F746_PJ14_FUNC_LCD_B2>,
-			       <STM32F746_PJ15_FUNC_LCD_B3>,
-			       <STM32F746_PK0_FUNC_LCD_G5>,
-			       <STM32F746_PK1_FUNC_LCD_G6>,
-			       <STM32F746_PK2_FUNC_LCD_G7>,
-			       <STM32F746_PK4_FUNC_LCD_B5>,
-			       <STM32F746_PK5_FUNC_LCD_B6>,
-			       <STM32F746_PK6_FUNC_LCD_B7>,
-			       <STM32F746_PK7_FUNC_LCD_DE>;
-			slew-rate = <2>;
-		};
-	};
-};
-
-&usart1 {
-	pinctrl-0 = <&usart1_pins_a>;
+&i2c1 {
+	pinctrl-0 = <&i2c1_pins_b>;
 	pinctrl-names = "default";
+	i2c-scl-rising-time-ns = <185>;
+	i2c-scl-falling-time-ns = <20>;
 	status = "okay";
 };
 
-&fmc {
-	pinctrl-0 = <&fmc_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
-	bank1: bank@0 {
-	       st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_4
-	       				    CAS_3 SDCLK_2 RD_BURST_EN
-					    RD_PIPE_DL_0>;
-	       st,sdram-timing = /bits/ 8 <TMRD_2 TXSR_6 TRAS_4 TRC_6 TWR_2
-	       				   TRP_2 TRCD_2>;
-		/* refcount = (64msec/total_row_sdram)*freq - 20 */
-	       st,sdram-refcount = < 1542 >;
-       };
-};
-
-&mac {
+&sdio1 {
 	status = "okay";
-	pinctrl-0 = <&ethernet_mii>;
-	phy-mode = "rmii";
-	phy-handle = <&phy0>;
-
-	mdio0 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "snps,dwmac-mdio";
-		phy0: ethernet-phy@0 {
-			reg = <0>;
-		};
-	};
+	vmmc-supply = <&mmc_vcard>;
+	cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default", "opendrain";
+	pinctrl-0 = <&sdio_pins_a>;
+	pinctrl-1 = <&sdio_pins_od_a>;
+	bus-width = <4>;
 };
 
-&qspi {
-	pinctrl-0 = <&qspi_pins>;
+&usart1 {
+	pinctrl-0 = <&usart1_pins_b>;
+	pinctrl-names = "default";
 	status = "okay";
-
-	qflash0: n25q128a {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "micron,n25q128a13", "jedec,spi-nor";
-			spi-max-frequency = <108000000>;
-			spi-tx-bus-width = <1>;
-			spi-rx-bus-width = <1>;
-			memory-map = <0x90000000 0x1000000>;
-			reg = <0>;
-	};
 };
 
-&sdio {
+&usbotg_fs {
+	dr_mode = "host";
+	pinctrl-0 = <&usbotg_fs_pins_a>;
+	pinctrl-names = "default";
 	status = "okay";
-	cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
-	pinctrl-names = "default", "opendrain";
-	pinctrl-0 = <&sdio_pins>;
-	pinctrl-1 = <&sdio_pins_od>;
-	bus-width = <4>;
-	max-frequency = <25000000>;
 };
 
-&ltdc {
+&usbotg_hs {
+	dr_mode = "host";
+	phys = <&usbotg_hs_phy>;
+	phy-names = "usb2-phy";
+	pinctrl-0 = <&usbotg_hs_pins_b>;
+	pinctrl-names = "default";
 	status = "okay";
-	pinctrl-0 = <&ltdc_pins>;
 };
diff --git a/arch/arm/dts/stm32f746-pinctrl.dtsi b/arch/arm/dts/stm32f746-pinctrl.dtsi
new file mode 100644
index 00000000000..fcfd2ac7239
--- /dev/null
+++ b/arch/arm/dts/stm32f746-pinctrl.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Alexandre Torgue  <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+#include "stm32f7-pinctrl.dtsi"
+
+&pinctrl{
+	compatible = "st,stm32f746-pinctrl";
+};
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index afa7832f893..f48d06a80d1 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -1,9 +1,4 @@
 /*
- * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
- * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
- *
- * Based on:
- * stm32f429.dtsi from Linux
  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
  *
  * This file is dual-licensed: you can use it either under the terms
@@ -45,8 +40,8 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include "skeleton.dtsi"
 #include "armv7-m.dtsi"
-#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
 #include <dt-bindings/clock/stm32fx-clock.h>
 #include <dt-bindings/mfd/stm32f7-rcc.h>
 
@@ -57,292 +52,584 @@
 			compatible = "fixed-clock";
 			clock-frequency = <0>;
 		};
-};
+
+		clk-lse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+		};
+
+		clk-lsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+		};
+
+		clk_i2s_ckin: clk-i2s-ckin {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <48000000>;
+		};
+	};
 
 	soc {
-		u-boot,dm-pre-reloc;
-		mac: ethernet@40028000 {
-			compatible = "st,stm32-dwmac";
-			reg = <0x40028000 0x8000>;
-			reg-names = "stmmaceth";
-			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
-				 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
-				 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
-			interrupts = <61>, <62>;
-			interrupt-names = "macirq", "eth_wake_irq";
-			snps,pbl = <8>;
-			snps,mixed-burst;
-			dma-ranges;
-			status = "disabled";
-		};
-
-		fmc: fmc@A0000000 {
-			compatible = "st,stm32-fmc";
-			reg = <0xA0000000 0x1000>;
-			clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
-			u-boot,dm-pre-reloc;
-		};
-
-		qspi: quadspi@A0001000 {
-			compatible = "st,stm32-qspi";
+		timer2: timer@40000000 {
+			compatible = "st,stm32-timer";
+			reg = <0x40000000 0x400>;
+			interrupts = <28>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
+			status = "disabled";
+		};
+
+		timers2: timers@40000000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
-			reg-names = "qspi", "qspi_mm";
-			interrupts = <92>;
-			spi-max-frequency = <108000000>;
-			clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
-			resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
+			clock-names = "int";
 			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+			};
+
+			timer@1 {
+				compatible = "st,stm32-timer-trigger";
+				reg = <1>;
+				status = "disabled";
+			};
 		};
-		usart1: serial@40011000 {
-			compatible = "st,stm32f7-usart", "st,stm32f7-uart";
-			reg = <0x40011000 0x400>;
-			interrupts = <37>;
-			clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
+
+		timer3: timer@40000400 {
+			compatible = "st,stm32-timer";
+			reg = <0x40000400 0x400>;
+			interrupts = <29>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
 			status = "disabled";
-			u-boot,dm-pre-reloc;
 		};
 
-		pwrcfg: power-config@58024800 {
-			compatible = "syscon";
-			reg = <0x40007000 0x400>;
+		timers3: timers@40000400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40000400 0x400>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+			};
+
+			timer@2 {
+				compatible = "st,stm32-timer-trigger";
+				reg = <2>;
+				status = "disabled";
+			};
 		};
 
-		rcc: rcc@40023810 {
-			#reset-cells = <1>;
-			#clock-cells = <2>;
-			compatible = "st,stm32f746-rcc", "st,stm32-rcc";
-			reg = <0x40023800 0x400>;
-			clocks = <&clk_hse>;
-			st,syscfg = <&pwrcfg>;
-			u-boot,dm-pre-reloc;
+		timer4: timer@40000800 {
+			compatible = "st,stm32-timer";
+			reg = <0x40000800 0x400>;
+			interrupts = <30>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
+			status = "disabled";
 		};
 
-		pinctrl: pin-controller {
+		timers4: timers@40000800 {
 			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "st,stm32f746-pinctrl";
-			ranges = <0 0x40020000 0x3000>;
-			u-boot,dm-pre-reloc;
-			pins-are-numbered;
-
-			gpioa: gpio@40020000 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
-				reg = <0x0 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
-				st,bank-name = "GPIOA";
-				u-boot,dm-pre-reloc;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40000800 0x400>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
 			};
 
-			gpiob: gpio@40020400 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
-				reg = <0x400 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
-				st,bank-name = "GPIOB";
-				u-boot,dm-pre-reloc;
+			timer@3 {
+				compatible = "st,stm32-timer-trigger";
+				reg = <3>;
+				status = "disabled";
 			};
+		};
+
+		timer5: timer@40000c00 {
+			compatible = "st,stm32-timer";
+			reg = <0x40000c00 0x400>;
+			interrupts = <50>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
+		};
 
+		timers5: timers@40000c00 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40000C00 0x400>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
+			clock-names = "int";
+			status = "disabled";
 
-			gpioc: gpio@40020800 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
-				reg = <0x800 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
-				st,bank-name = "GPIOC";
-				u-boot,dm-pre-reloc;
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
 			};
 
-			gpiod: gpio@40020c00 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
-				reg = <0xc00 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
-				st,bank-name = "GPIOD";
-				u-boot,dm-pre-reloc;
+			timer@4 {
+				compatible = "st,stm32-timer-trigger";
+				reg = <4>;
+				status = "disabled";
 			};
+		};
 
-			gpioe: gpio@40021000 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
-				reg = <0x1000 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
-				st,bank-name = "GPIOE";
-				u-boot,dm-pre-reloc;
-			};
+		timer6: timer@40001000 {
+			compatible = "st,stm32-timer";
+			reg = <0x40001000 0x400>;
+			interrupts = <54>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
+			status = "disabled";
+		};
+
+		timers6: timers@40001000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40001000 0x400>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
+			clock-names = "int";
+			status = "disabled";
 
-			gpiof: gpio@40021400 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
-				reg = <0x1400 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
-				st,bank-name = "GPIOF";
-				u-boot,dm-pre-reloc;
+			timer@5 {
+				compatible = "st,stm32-timer-trigger";
+				reg = <5>;
+				status = "disabled";
 			};
+		};
 
-			gpiog: gpio@40021800 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
-				reg = <0x1800 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
-				st,bank-name = "GPIOG";
-				u-boot,dm-pre-reloc;
+		timer7: timer@40001400 {
+			compatible = "st,stm32-timer";
+			reg = <0x40001400 0x400>;
+			interrupts = <55>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
+			status = "disabled";
+		};
+
+		timers7: timers@40001400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40001400 0x400>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
+			clock-names = "int";
+			status = "disabled";
+
+			timer@6 {
+				compatible = "st,stm32-timer-trigger";
+				reg = <6>;
+				status = "disabled";
 			};
+		};
+
+		timers12: timers@40001800 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40001800 0x400>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
+			clock-names = "int";
+			status = "disabled";
 
-			gpioh: gpio@40021c00 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
-				reg = <0x1c00 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
-				st,bank-name = "GPIOH";
-				u-boot,dm-pre-reloc;
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
 			};
 
-			gpioi: gpio@40022000 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
-				reg = <0x2000 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
-				st,bank-name = "GPIOI";
-				u-boot,dm-pre-reloc;
+			timer@11 {
+				compatible = "st,stm32-timer-trigger";
+				reg = <11>;
+				status = "disabled";
 			};
+		};
 
-			gpioj: gpio@40022400 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
-				reg = <0x2400 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
-				st,bank-name = "GPIOJ";
-				u-boot,dm-pre-reloc;
+		timers13: timers@40001c00 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40001C00 0x400>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
 			};
+		};
 
-			gpiok: gpio@40022800 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
-				reg = <0x2800 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
-				st,bank-name = "GPIOK";
-				u-boot,dm-pre-reloc;
+		timers14: timers@40002000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40002000 0x400>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
 			};
+		};
+
+		rtc: rtc@40002800 {
+			compatible = "st,stm32-rtc";
+			reg = <0x40002800 0x400>;
+			clocks = <&rcc 1 CLK_RTC>;
+			clock-names = "ck_rtc";
+			assigned-clocks = <&rcc 1 CLK_RTC>;
+			assigned-clock-parents = <&rcc 1 CLK_LSE>;
+			interrupt-parent = <&exti>;
+			interrupts = <17 1>;
+			interrupt-names = "alarm";
+			st,syscfg = <&pwrcfg 0x00 0x100>;
+			status = "disabled";
+		};
+
+		usart2: serial@40004400 {
+			compatible = "st,stm32f7-uart";
+			reg = <0x40004400 0x400>;
+			interrupts = <38>;
+			clocks = <&rcc 1 CLK_USART2>;
+			status = "disabled";
+		};
+
+		usart3: serial@40004800 {
+			compatible = "st,stm32f7-uart";
+			reg = <0x40004800 0x400>;
+			interrupts = <39>;
+			clocks = <&rcc 1 CLK_USART3>;
+			status = "disabled";
+		};
+
+		usart4: serial@40004c00 {
+			compatible = "st,stm32f7-uart";
+			reg = <0x40004c00 0x400>;
+			interrupts = <52>;
+			clocks = <&rcc 1 CLK_UART4>;
+			status = "disabled";
+		};
+
+		usart5: serial@40005000 {
+			compatible = "st,stm32f7-uart";
+			reg = <0x40005000 0x400>;
+			interrupts = <53>;
+			clocks = <&rcc 1 CLK_UART5>;
+			status = "disabled";
+		};
 
-			sdio_pins: sdio_pins@0 {
-				pins {
-					pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
-						 <STM32F746_PC9_FUNC_SDMMC1_D1>,
-						 <STM32F746_PC10_FUNC_SDMMC1_D2>,
-						 <STM32F746_PC11_FUNC_SDMMC1_D3>,
-						 <STM32F746_PC12_FUNC_SDMMC1_CK>,
-						 <STM32F746_PD2_FUNC_SDMMC1_CMD>;
-					drive-push-pull;
-					slew-rate = <2>;
-				};
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32f7-i2c";
+			reg = <0x40005400 0x400>;
+			interrupts = <31>,
+				     <32>;
+			resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
+			clocks = <&rcc 1 CLK_I2C1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32f7-i2c";
+			reg = <0x40005800 0x400>;
+			interrupts = <33>,
+				     <34>;
+			resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
+			clocks = <&rcc 1 CLK_I2C2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@40005C00 {
+			compatible = "st,stm32f7-i2c";
+			reg = <0x40005C00 0x400>;
+			interrupts = <72>,
+				     <73>;
+			resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
+			clocks = <&rcc 1 CLK_I2C3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@40006000 {
+			compatible = "st,stm32f7-i2c";
+			reg = <0x40006000 0x400>;
+			interrupts = <95>,
+				     <96>;
+			resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
+			clocks = <&rcc 1 CLK_I2C4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		cec: cec@40006c00 {
+			compatible = "st,stm32-cec";
+			reg = <0x40006C00 0x400>;
+			interrupts = <94>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
+			clock-names = "cec", "hdmi-cec";
+			status = "disabled";
+		};
+
+		usart7: serial@40007800 {
+			compatible = "st,stm32f7-uart";
+			reg = <0x40007800 0x400>;
+			interrupts = <82>;
+			clocks = <&rcc 1 CLK_UART7>;
+			status = "disabled";
+		};
+
+		usart8: serial@40007c00 {
+			compatible = "st,stm32f7-uart";
+			reg = <0x40007c00 0x400>;
+			interrupts = <83>;
+			clocks = <&rcc 1 CLK_UART8>;
+			status = "disabled";
+		};
+
+		timers1: timers@40010000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40010000 0x400>;
+			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
 			};
 
-			sdio_pins_od: sdio_pins_od@0 {
-				pins1 {
-					pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
-						 <STM32F746_PC9_FUNC_SDMMC1_D1>,
-						 <STM32F746_PC10_FUNC_SDMMC1_D2>,
-						 <STM32F746_PC11_FUNC_SDMMC1_D3>,
-						 <STM32F746_PC12_FUNC_SDMMC1_CK>;
-					drive-push-pull;
-					slew-rate = <2>;
-				};
-
-				pins2 {
-					pinmux = <STM32F746_PD2_FUNC_SDMMC1_CMD>;
-					drive-open-drain;
-					slew-rate = <2>;
-				};
+			timer@0 {
+				compatible = "st,stm32-timer-trigger";
+				reg = <0>;
+				status = "disabled";
 			};
+		};
 
-			sdio_pins_b: sdio_pins_b@0 {
-				pins {
-					pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
-						 <STM32F769_PG10_FUNC_SDMMC2_D1>,
-						 <STM32F769_PB3_FUNC_SDMMC2_D2>,
-						 <STM32F769_PB4_FUNC_SDMMC2_D3>,
-						 <STM32F769_PD6_FUNC_SDMMC2_CLK>,
-						 <STM32F769_PD7_FUNC_SDMMC2_CMD>;
-					drive-push-pull;
-					slew-rate = <2>;
-				};
+		timers8: timers@40010400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40010400 0x400>;
+			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
 			};
 
-			sdio_pins_od_b: sdio_pins_od_b@0 {
-				pins1 {
-					pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
-						 <STM32F769_PG10_FUNC_SDMMC2_D1>,
-						 <STM32F769_PB3_FUNC_SDMMC2_D2>,
-						 <STM32F769_PB4_FUNC_SDMMC2_D3>,
-						 <STM32F769_PD6_FUNC_SDMMC2_CLK>;
-					drive-push-pull;
-					slew-rate = <2>;
-				};
-
-				pins2 {
-					pinmux = <STM32F769_PD7_FUNC_SDMMC2_CMD>;
-					drive-open-drain;
-					slew-rate = <2>;
-				};
+			timer@7 {
+				compatible = "st,stm32-timer-trigger";
+				reg = <7>;
+				status = "disabled";
 			};
+		};
 
+		usart1: serial@40011000 {
+			compatible = "st,stm32f7-uart";
+			reg = <0x40011000 0x400>;
+			interrupts = <37>;
+			clocks = <&rcc 1 CLK_USART1>;
+			status = "disabled";
 		};
-		sdio: sdio@40012c00 {
-			compatible = "st,stm32f4xx-sdio";
-			reg = <0x40012c00 0x400>;
-			clocks = <&rcc 0 171>;
-			interrupts = <49>;
+
+		usart6: serial@40011400 {
+			compatible = "st,stm32f7-uart";
+			reg = <0x40011400 0x400>;
+			interrupts = <71>;
+			clocks = <&rcc 1 CLK_USART6>;
 			status = "disabled";
-			pinctrl-0 = <&sdio_pins>;
-			pinctrl-1 = <&sdio_pins_od>;
-			pinctrl-names = "default", "opendrain";
-			max-frequency = <48000000>;
 		};
 
 		sdio2: sdio2@40011c00 {
-			compatible = "st,stm32f4xx-sdio";
+			compatible = "arm,pl180", "arm,primecell";
+			arm,primecell-periphid = <0x00880180>;
 			reg = <0x40011c00 0x400>;
-			clocks = <&rcc 0 167>;
+			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
+			clock-names = "apb_pclk";
 			interrupts = <103>;
+			max-frequency = <48000000>;
 			status = "disabled";
-			pinctrl-0 = <&sdio_pins_b>;
-			pinctrl-1 = <&sdio_pins_od_b>;
-			pinctrl-names = "default", "opendrain";
+		};
+
+		sdio1: sdio1@40012c00 {
+			compatible = "arm,pl180", "arm,primecell";
+			arm,primecell-periphid = <0x00880180>;
+			reg = <0x40012c00 0x400>;
+			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
+			clock-names = "apb_pclk";
+			interrupts = <49>;
 			max-frequency = <48000000>;
+			status = "disabled";
 		};
 
-		timer5: timer@40000c00 {
-			compatible = "st,stm32-timer";
-			reg = <0x40000c00 0x400>;
-			interrupts = <50>;
-			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
+		syscfg: system-config@40013800 {
+			compatible = "syscon";
+			reg = <0x40013800 0x400>;
+		};
+
+		exti: interrupt-controller@40013c00 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x40013C00 0x400>;
+			interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
+		};
+
+		timers9: timers@40014000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40014000 0x400>;
+			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+			};
+
+			timer@8 {
+				compatible = "st,stm32-timer-trigger";
+				reg = <8>;
+				status = "disabled";
+			};
+		};
+
+		timers10: timers@40014400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40014400 0x400>;
+			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+			};
+		};
+
+		timers11: timers@40014800 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40014800 0x400>;
+			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+			};
+		};
+
+		pwrcfg: power-config@40007000 {
+			compatible = "syscon";
+			reg = <0x40007000 0x400>;
+		};
+
+		crc: crc@40023000 {
+			compatible = "st,stm32f7-crc";
+			reg = <0x40023000 0x400>;
+			clocks = <&rcc 0 12>;
+			status = "disabled";
+		};
+
+		rcc: rcc@40023800 {
+			#reset-cells = <1>;
+			#clock-cells = <2>;
+			compatible = "st,stm32f746-rcc", "st,stm32-rcc";
+			reg = <0x40023800 0x400>;
+			clocks = <&clk_hse>, <&clk_i2s_ckin>;
+			st,syscfg = <&pwrcfg>;
+			assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
+			assigned-clock-rates = <1000000>;
+		};
+
+		dma1: dma@40026000 {
+			compatible = "st,stm32-dma";
+			reg = <0x40026000 0x400>;
+			interrupts = <11>,
+				     <12>,
+				     <13>,
+				     <14>,
+				     <15>,
+				     <16>,
+				     <17>,
+				     <47>;
+			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
+			#dma-cells = <4>;
+			status = "disabled";
+		};
+
+		dma2: dma@40026400 {
+			compatible = "st,stm32-dma";
+			reg = <0x40026400 0x400>;
+			interrupts = <56>,
+				     <57>,
+				     <58>,
+				     <59>,
+				     <60>,
+				     <68>,
+				     <69>,
+				     <70>;
+			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
+			#dma-cells = <4>;
+			st,mem2mem;
+			status = "disabled";
+		};
+
+		usbotg_hs: usb@40040000 {
+			compatible = "st,stm32f7-hsotg";
+			reg = <0x40040000 0x40000>;
+			interrupts = <77>;
+			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
+			clock-names = "otg";
+			g-rx-fifo-size = <256>;
+			g-np-tx-fifo-size = <32>;
+			g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
+			status = "disabled";
 		};
 
-		ltdc: display-controller@40016800 {
-			compatible = "st,stm32-ltdc";
-			reg = <0x40016800 0x200>;
-			resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
-			clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
-			u-boot,dm-pre-reloc;
+		usbotg_fs: usb@50000000 {
+			compatible = "st,stm32f4x9-fsotg";
+			reg = <0x50000000 0x40000>;
+			interrupts = <67>;
+			clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
+			clock-names = "otg";
 			status = "disabled";
 		};
 	};
 };
 
 &systick {
+	clocks = <&rcc 1 0>;
 	status = "okay";
 };
diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi
new file mode 100644
index 00000000000..e9e43cba10b
--- /dev/null
+++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <stm32f7-u-boot.dtsi>
+/{
+	chosen {
+		bootargs = "root=/dev/ram rdinit=/linuxrc";
+	};
+
+	aliases {
+		/* Aliases for gpios so as to use sequence */
+		gpio0 = &gpioa;
+		gpio1 = &gpiob;
+		gpio2 = &gpioc;
+		gpio3 = &gpiod;
+		gpio4 = &gpioe;
+		gpio5 = &gpiof;
+		gpio6 = &gpiog;
+		gpio7 = &gpioh;
+		gpio8 = &gpioi;
+		gpio9 = &gpioj;
+		gpio10 = &gpiok;
+		mmc0 = &sdio2;
+		spi0 = &qspi;
+	};
+
+	button1 {
+		compatible = "st,button1";
+		button-gpio = <&gpioa 0 0>;
+	};
+
+	led1 {
+		compatible = "st,led1";
+		led-gpio = <&gpioj 5 0>;
+	};
+};
+
+&fmc {
+	/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
+	bank1: bank@0 {
+		u-boot,dm-pre-reloc;
+		st,sdram-control = /bits/ 8 <NO_COL_8
+					     NO_ROW_12
+					     MWIDTH_32
+					     BANKS_4
+					     CAS_3
+					     SDCLK_2
+					     RD_BURST_EN
+					     RD_PIPE_DL_0>;
+		st,sdram-timing = /bits/ 8 <TMRD_2
+					    TXSR_6
+					    TRAS_4
+					    TRC_6
+					    TWR_2
+					    TRP_2
+					    TRCD_2>;
+		/* refcount = (64msec/total_row_sdram)*freq - 20 */
+		st,sdram-refcount = < 1542 >;
+	};
+};
+
+&pinctrl {
+	ethernet_mii: mii@0 {
+		pins {
+			pinmux = <STM32_PINMUX('G',13, AF11)>, /* ETH_RMII_TXD0 */
+				 <STM32_PINMUX('G',14, AF11)>, /* ETH_RMII_TXD1 */
+				 <STM32_PINMUX('G',11, AF11)>, /* ETH_RMII_TX_EN */
+				 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
+				 <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
+				 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
+				 <STM32_PINMUX('A', 7, AF11)>, /* ETH_RMII_CRS_DV */
+				 <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
+				 <STM32_PINMUX('C', 5, AF11)>; /* ETH_RMII_RXD1 */
+			slew-rate = <2>;
+		};
+	};
+
+	fmc_pins: fmc@0 {
+		pins {
+			pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
+				 <STM32_PINMUX('I', 9, AF12)>, /* D30 */
+				 <STM32_PINMUX('I', 7, AF12)>, /* D29 */
+				 <STM32_PINMUX('I', 6, AF12)>, /* D28 */
+				 <STM32_PINMUX('I', 3, AF12)>, /* D27 */
+				 <STM32_PINMUX('I', 2, AF12)>, /* D26 */
+				 <STM32_PINMUX('I', 1, AF12)>, /* D25 */
+				 <STM32_PINMUX('I', 0, AF12)>, /* D24 */
+				 <STM32_PINMUX('H',15, AF12)>, /* D23 */
+				 <STM32_PINMUX('H',14, AF12)>, /* D22 */
+				 <STM32_PINMUX('H',13, AF12)>, /* D21 */
+				 <STM32_PINMUX('H',12, AF12)>, /* D20 */
+				 <STM32_PINMUX('H',11, AF12)>, /* D19 */
+				 <STM32_PINMUX('H',10, AF12)>, /* D18 */
+				 <STM32_PINMUX('H', 9, AF12)>, /* D17 */
+				 <STM32_PINMUX('H', 8, AF12)>, /* D16 */
+
+				 <STM32_PINMUX('D',10, AF12)>, /* D15 */
+				 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
+				 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
+				 <STM32_PINMUX('E',15, AF12)>, /* D12 */
+				 <STM32_PINMUX('E',14, AF12)>, /* D11 */
+				 <STM32_PINMUX('E',13, AF12)>, /* D10 */
+				 <STM32_PINMUX('E',12, AF12)>, /* D9 */
+				 <STM32_PINMUX('E',11, AF12)>, /* D8 */
+				 <STM32_PINMUX('E',10, AF12)>, /* D7 */
+				 <STM32_PINMUX('E', 9, AF12)>, /* D6 */
+				 <STM32_PINMUX('E', 8, AF12)>, /* D5 */
+				 <STM32_PINMUX('E', 7, AF12)>, /* D4 */
+				 <STM32_PINMUX('D', 1, AF12)>, /* D3 */
+				 <STM32_PINMUX('D', 0, AF12)>, /* D2 */
+				 <STM32_PINMUX('D',15, AF12)>, /* D1 */
+				 <STM32_PINMUX('D',14, AF12)>, /* D0 */
+
+				 <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
+				 <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
+				 <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
+				 <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
+
+				 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
+				 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
+
+				 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
+				 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
+				 <STM32_PINMUX('F',15, AF12)>, /* A9 */
+				 <STM32_PINMUX('F',14, AF12)>, /* A8 */
+				 <STM32_PINMUX('F',13, AF12)>, /* A7 */
+				 <STM32_PINMUX('F',12, AF12)>, /* A6 */
+				 <STM32_PINMUX('F', 5, AF12)>, /* A5 */
+				 <STM32_PINMUX('F', 4, AF12)>, /* A4 */
+				 <STM32_PINMUX('F', 3, AF12)>, /* A3 */
+				 <STM32_PINMUX('F', 2, AF12)>, /* A2 */
+				 <STM32_PINMUX('F', 1, AF12)>, /* A1 */
+				 <STM32_PINMUX('F', 0, AF12)>, /* A0 */
+
+				 <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
+				 <STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
+				 <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
+				 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
+				 <STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
+				 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
+			slew-rate = <2>;
+		};
+	};
+
+	qspi_pins: qspi@0 {
+		pins {
+			pinmux = <STM32_PINMUX('B', 2, AF9)>, /* CLK */
+				 <STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */
+				 <STM32_PINMUX('C', 9, AF9)>, /* BK1_IO0 */
+				 <STM32_PINMUX('C',10, AF9)>, /* BK1_IO1 */
+				 <STM32_PINMUX('D',13, AF9)>, /* BK1_IO3 */
+				 <STM32_PINMUX('E', 2, AF9)>; /* BK1_IO2 */
+			slew-rate = <2>;
+		};
+	};
+};
+
+&qspi {
+	flash0: mx66l51235l {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <108000000>;
+		spi-rx-bus-width = <4>;
+		reg = <0>;
+	};
+};
diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts
index a23d02d3008..483d896e2bc 100644
--- a/arch/arm/dts/stm32f769-disco.dts
+++ b/arch/arm/dts/stm32f769-disco.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 - Vikas Manocha <vikas.manocha@st.com>
+ * Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -42,15 +42,16 @@
 
 /dts-v1/;
 #include "stm32f746.dtsi"
-#include <dt-bindings/memory/stm32-sdram.h>
+#include "stm32f769-pinctrl.dtsi"
+#include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "STMicroelectronics STM32F769-DISCO board";
-	compatible = "st,stm32f769-disco", "st,stm32f7";
+	compatible = "st,stm32f769-disco", "st,stm32f769";
 
 	chosen {
-		bootargs = "root=/dev/ram rdinit=/linuxrc";
+		bootargs = "root=/dev/ram";
 		stdout-path = "serial0:115200n8";
 	};
 
@@ -60,207 +61,90 @@
 
 	aliases {
 		serial0 = &usart1;
-		spi0 = &qspi;
-		mmc0 = &sdio2;
-		/* Aliases for gpios so as to use sequence */
-		gpio0 = &gpioa;
-		gpio1 = &gpiob;
-		gpio2 = &gpioc;
-		gpio3 = &gpiod;
-		gpio4 = &gpioe;
-		gpio5 = &gpiof;
-		gpio6 = &gpiog;
-		gpio7 = &gpioh;
-		gpio8 = &gpioi;
-		gpio9 = &gpioj;
-		gpio10 = &gpiok;
 	};
 
-	led1 {
-		compatible = "st,led1";
-		led-gpio = <&gpioj 5 0>;
-	};
-
-	button1 {
-		compatible = "st,button1";
-		button-gpio = <&gpioa 0 0>;
-	};
-};
-
-&clk_hse {
-	clock-frequency = <25000000>;
-};
-
-&pinctrl {
-	usart1_pins_a: usart1@0	{
-		pins1 {
-		       pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
-				bias-disable;
-				drive-push-pull;
-				slew-rate = <2>;
+	leds {
+		compatible = "gpio-leds";
+		green {
+			gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
 		};
-		pins2 {
-			pinmux = <STM32F746_PA10_FUNC_USART1_RX>;
-			bias-disable;
+		red {
+			gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>;
 		};
 	};
 
-	ethernet_mii: mii@0 {
-	      pins {
-		      pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
-			     <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
-			     <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
-			     <STM32F746_PA2_FUNC_ETH_MDIO>,
-			     <STM32F746_PC1_FUNC_ETH_MDC>,
-			     <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
-			     <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
-			     <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
-			     <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
-		      slew-rate = <2>;
-	      };
-	};
-
-	qspi_pins: qspi@0 {
-		pins {
-			pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
-			       <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
-			       <STM32F746_PC9_FUNC_QUADSPI_BK1_IO0>,
-			       <STM32F746_PC10_FUNC_QUADSPI_BK1_IO1>,
-			       <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
-			       <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
-			slew-rate = <2>;
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+		button@0 {
+			label = "User";
+			linux,code = <KEY_HOME>;
+			gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
 		};
 	};
 
-	fmc_pins: fmc@0 {
-		  pins {
-			  pinmux = <STM32F746_PI10_FUNC_FMC_D31>,
-				 <STM32F746_PI9_FUNC_FMC_D30>,
-				 <STM32F746_PI7_FUNC_FMC_D29>,
-				 <STM32F746_PI6_FUNC_FMC_D28>,
-				 <STM32F746_PI3_FUNC_FMC_D27>,
-				 <STM32F746_PI2_FUNC_FMC_D26>,
-				 <STM32F746_PI1_FUNC_FMC_D25>,
-				 <STM32F746_PI0_FUNC_FMC_D24>,
-				 <STM32F746_PH15_FUNC_FMC_D23>,
-				 <STM32F746_PH14_FUNC_FMC_D22>,
-				 <STM32F746_PH13_FUNC_FMC_D21>,
-				 <STM32F746_PH12_FUNC_FMC_D20>,
-				 <STM32F746_PH11_FUNC_FMC_D19>,
-				 <STM32F746_PH10_FUNC_FMC_D18>,
-				 <STM32F746_PH9_FUNC_FMC_D17>,
-				 <STM32F746_PH8_FUNC_FMC_D16>,
-
-				 <STM32F746_PD10_FUNC_FMC_D15>,
-				 <STM32F746_PD9_FUNC_FMC_D14>,
-				 <STM32F746_PD8_FUNC_FMC_D13>,
-				 <STM32F746_PE15_FUNC_FMC_D12>,
-				 <STM32F746_PE14_FUNC_FMC_D11>,
-				 <STM32F746_PE13_FUNC_FMC_D10>,
-				 <STM32F746_PE12_FUNC_FMC_D9>,
-				 <STM32F746_PE11_FUNC_FMC_D8>,
-				 <STM32F746_PE10_FUNC_FMC_D7>,
-				 <STM32F746_PE9_FUNC_FMC_D6>,
-				 <STM32F746_PE8_FUNC_FMC_D5>,
-				 <STM32F746_PE7_FUNC_FMC_D4>,
-				 <STM32F746_PD1_FUNC_FMC_D3>,
-				 <STM32F746_PD0_FUNC_FMC_D2>,
-				 <STM32F746_PD15_FUNC_FMC_D1>,
-				 <STM32F746_PD14_FUNC_FMC_D0>,
-
-				 <STM32F746_PI5_FUNC_FMC_NBL3>,
-				 <STM32F746_PI4_FUNC_FMC_NBL2>,
-				 <STM32F746_PE1_FUNC_FMC_NBL1>,
-				 <STM32F746_PE0_FUNC_FMC_NBL0>,
-
-				 <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
-				 <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
-
-				 <STM32F746_PG1_FUNC_FMC_A11>,
-				 <STM32F746_PG0_FUNC_FMC_A10>,
-				 <STM32F746_PF15_FUNC_FMC_A9>,
-				 <STM32F746_PF14_FUNC_FMC_A8>,
-				 <STM32F746_PF13_FUNC_FMC_A7>,
-				 <STM32F746_PF12_FUNC_FMC_A6>,
-				 <STM32F746_PF5_FUNC_FMC_A5>,
-				 <STM32F746_PF4_FUNC_FMC_A4>,
-				 <STM32F746_PF3_FUNC_FMC_A3>,
-				 <STM32F746_PF2_FUNC_FMC_A2>,
-				 <STM32F746_PF1_FUNC_FMC_A1>,
-				 <STM32F746_PF0_FUNC_FMC_A0>,
+	usbotg_hs_phy: usb-phy {
+		#phy-cells = <0>;
+		compatible = "usb-nop-xceiv";
+		clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
+		clock-names = "main_clk";
+	};
 
-				 <STM32F746_PH3_FUNC_FMC_SDNE0>,
-				 <STM32F746_PH5_FUNC_FMC_SDNWE>,
-				 <STM32F746_PF11_FUNC_FMC_SDNRAS>,
-				 <STM32F746_PG15_FUNC_FMC_SDNCAS>,
-				 <STM32F746_PH2_FUNC_FMC_SDCKE0>,
-				 <STM32F746_PG8_FUNC_FMC_SDCLK>;
-			  slew-rate = <2>;
-		  };
-	  };
+	mmc_vcard: mmc_vcard {
+		compatible = "regulator-fixed";
+		regulator-name = "mmc_vcard";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
 };
 
-&usart1 {
-	pinctrl-0 = <&usart1_pins_a>;
+&cec {
+	pinctrl-0 = <&cec_pins_a>;
 	pinctrl-names = "default";
 	status = "okay";
 };
 
-&fmc {
-	pinctrl-0 = <&fmc_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
-	bank1: bank@0 {
-	       st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_32 BANKS_4
-	       				    CAS_3 SDCLK_2 RD_BURST_EN
-					    RD_PIPE_DL_0>;
-	       st,sdram-timing = /bits/ 8 <TMRD_2 TXSR_6 TRAS_4 TRC_6 TWR_2
-	       				   TRP_2 TRCD_2>;
-		/* refcount = (64msec/total_row_sdram)*freq - 20 */
-	       st,sdram-refcount = < 1542 >;
-       };
+&clk_hse {
+	clock-frequency = <25000000>;
 };
 
-&mac {
+&i2c1 {
+	pinctrl-0 = <&i2c1_pins_b>;
+	pinctrl-names = "default";
+	i2c-scl-rising-time-ns = <185>;
+	i2c-scl-falling-time-ns = <20>;
 	status = "okay";
-	pinctrl-0 = <&ethernet_mii>;
-	phy-mode = "rmii";
-	phy-handle = <&phy0>;
-
-	mdio0 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "snps,dwmac-mdio";
-		phy0: ethernet-phy@0 {
-			reg = <0>;
-		};
-	};
 };
 
-&qspi {
-	pinctrl-0 = <&qspi_pins>;
+&rtc {
 	status = "okay";
-
-	qflash0: n25q128a {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "micron,n25q128a13", "jedec,spi-nor";
-			spi-max-frequency = <108000000>;
-			spi-tx-bus-width = <1>;
-			spi-rx-bus-width = <1>;
-			memory-map = <0x90000000 0x1000000>;
-			reg = <0>;
-	};
 };
 
 &sdio2 {
 	status = "okay";
+	vmmc-supply = <&mmc_vcard>;
 	cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
+	broken-cd;
 	pinctrl-names = "default", "opendrain";
 	pinctrl-0 = <&sdio_pins_b>;
 	pinctrl-1 = <&sdio_pins_od_b>;
 	bus-width = <4>;
-	max-frequency = <25000000>;
+};
+
+&usart1 {
+	pinctrl-0 = <&usart1_pins_a>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usbotg_hs {
+	dr_mode = "otg";
+	phys = <&usbotg_hs_phy>;
+	phy-names = "usb2-phy";
+	pinctrl-0 = <&usbotg_hs_pins_a>;
+	pinctrl-names = "default";
+	status = "okay";
 };
diff --git a/arch/arm/dts/stm32f769-pinctrl.dtsi b/arch/arm/dts/stm32f769-pinctrl.dtsi
new file mode 100644
index 00000000000..31005dd9929
--- /dev/null
+++ b/arch/arm/dts/stm32f769-pinctrl.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Alexandre Torgue  <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+#include "stm32f7-pinctrl.dtsi"
+
+&pinctrl{
+	compatible = "st,stm32f769-pinctrl";
+};
diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi
index 2525035da19..99fa0e673a1 100644
--- a/arch/arm/dts/stm32h7-u-boot.dtsi
+++ b/arch/arm/dts/stm32h7-u-boot.dtsi
@@ -1,13 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <dt-bindings/memory/stm32-sdram.h>
+
 /{
 	clocks {
 		u-boot,dm-pre-reloc;
 	};
 
+	aliases {
+		gpio0 = &gpioa;
+		gpio1 = &gpiob;
+		gpio2 = &gpioc;
+		gpio3 = &gpiod;
+		gpio4 = &gpioe;
+		gpio5 = &gpiof;
+		gpio6 = &gpiog;
+		gpio7 = &gpioh;
+		gpio8 = &gpioi;
+		gpio9 = &gpioj;
+		gpio10 = &gpiok;
+		mmc0 = &sdmmc1;
+	};
+
 	soc {
 		u-boot,dm-pre-reloc;
 		pin-controller {
 			u-boot,dm-pre-reloc;
 		};
+
+		fmc: fmc@52004000 {
+			compatible = "st,stm32h7-fmc";
+			reg = <0x52004000 0x1000>;
+			clocks = <&rcc FMC_CK>;
+
+			pinctrl-0 = <&fmc_pins>;
+			pinctrl-names = "default";
+			status = "okay";
+
+			/*
+			 * Memory configuration from sdram datasheet IS42S32800G-6BLI
+			 * firsct bank is bank@0
+			 * second bank is bank@1
+			 */
+			bank1: bank@1 {
+				st,sdram-control = /bits/ 8 <NO_COL_9
+							     NO_ROW_12
+							     MWIDTH_32
+							     BANKS_4
+							     CAS_2
+							     SDCLK_3
+							     RD_BURST_EN
+							     RD_PIPE_DL_0>;
+				st,sdram-timing = /bits/ 8 <TMRD_1
+							    TXSR_1
+							    TRAS_1
+							    TRC_6
+							    TRP_2
+							    TWR_1
+							    TRCD_1>;
+				st,sdram-refcount = <1539>;
+			};
+		};
+
+		sdmmc1: sdmmc@52007000 {
+			compatible = "st,stm32-sdmmc2";
+			reg = <0x52007000 0x1000>;
+			interrupts = <49>;
+			clocks = <&rcc SDMMC1_CK>;
+			resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
+			st,idma = <1>;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+		};
 	};
 };
 
@@ -15,74 +79,175 @@
 	u-boot,dm-pre-reloc;
 };
 
-&clk_lse {
-	u-boot,dm-pre-reloc;
-};
-
 &clk_i2s {
 	u-boot,dm-pre-reloc;
 };
 
-&pwrcfg {
+&clk_lse {
 	u-boot,dm-pre-reloc;
 };
 
-&rcc {
-	u-boot,dm-pre-reloc;
-};
 
 &fmc {
 	u-boot,dm-pre-reloc;
 };
 
-&clk_hsi {
-	u-boot,dm-pre-reloc;
-};
-
-&clk_csi {
-	u-boot,dm-pre-reloc;
-};
-
 &gpioa {
 	u-boot,dm-pre-reloc;
+	compatible = "st,stm32-gpio";
 };
 
 &gpiob {
 	u-boot,dm-pre-reloc;
+	compatible = "st,stm32-gpio";
 };
 
 &gpioc {
 	u-boot,dm-pre-reloc;
+	compatible = "st,stm32-gpio";
 };
 
 &gpiod {
 	u-boot,dm-pre-reloc;
+	compatible = "st,stm32-gpio";
 };
 
 &gpioe {
 	u-boot,dm-pre-reloc;
+	compatible = "st,stm32-gpio";
 };
 
 &gpiof {
 	u-boot,dm-pre-reloc;
+	compatible = "st,stm32-gpio";
 };
 
 &gpiog {
 	u-boot,dm-pre-reloc;
+	compatible = "st,stm32-gpio";
 };
 
 &gpioh {
 	u-boot,dm-pre-reloc;
+	compatible = "st,stm32-gpio";
 };
 
 &gpioi {
 	u-boot,dm-pre-reloc;
+	compatible = "st,stm32-gpio";
 };
 
 &gpioj {
 	u-boot,dm-pre-reloc;
+	compatible = "st,stm32-gpio";
 };
 
 &gpiok {
 	u-boot,dm-pre-reloc;
+	compatible = "st,stm32-gpio";
+};
+
+&pinctrl {
+	fmc_pins: fmc@0 {
+		pins {
+			pinmux = <STM32_PINMUX('D', 0, AF12)>,
+				 <STM32_PINMUX('D', 1, AF12)>,
+				 <STM32_PINMUX('D', 8, AF12)>,
+				 <STM32_PINMUX('D', 9, AF12)>,
+				 <STM32_PINMUX('D',10, AF12)>,
+				 <STM32_PINMUX('D',14, AF12)>,
+				 <STM32_PINMUX('D',15, AF12)>,
+
+				 <STM32_PINMUX('E', 0, AF12)>,
+				 <STM32_PINMUX('E', 1, AF12)>,
+				 <STM32_PINMUX('E', 7, AF12)>,
+				 <STM32_PINMUX('E', 8, AF12)>,
+				 <STM32_PINMUX('E', 9, AF12)>,
+				 <STM32_PINMUX('E',10, AF12)>,
+				 <STM32_PINMUX('E',11, AF12)>,
+				 <STM32_PINMUX('E',12, AF12)>,
+				 <STM32_PINMUX('E',13, AF12)>,
+				 <STM32_PINMUX('E',14, AF12)>,
+				 <STM32_PINMUX('E',15, AF12)>,
+
+				 <STM32_PINMUX('F', 0, AF12)>,
+				 <STM32_PINMUX('F', 1, AF12)>,
+				 <STM32_PINMUX('F', 2, AF12)>,
+				 <STM32_PINMUX('F', 3, AF12)>,
+				 <STM32_PINMUX('F', 4, AF12)>,
+				 <STM32_PINMUX('F', 5, AF12)>,
+				 <STM32_PINMUX('F',11, AF12)>,
+				 <STM32_PINMUX('F',12, AF12)>,
+				 <STM32_PINMUX('F',13, AF12)>,
+				 <STM32_PINMUX('F',14, AF12)>,
+				 <STM32_PINMUX('F',15, AF12)>,
+
+				 <STM32_PINMUX('G', 0, AF12)>,
+				 <STM32_PINMUX('G', 1, AF12)>,
+				 <STM32_PINMUX('G', 2, AF12)>,
+				 <STM32_PINMUX('G', 4, AF12)>,
+				 <STM32_PINMUX('G', 5, AF12)>,
+				 <STM32_PINMUX('G', 8, AF12)>,
+				 <STM32_PINMUX('G',15, AF12)>,
+
+				 <STM32_PINMUX('H', 5, AF12)>,
+				 <STM32_PINMUX('H', 6, AF12)>,
+				 <STM32_PINMUX('H', 7, AF12)>,
+				 <STM32_PINMUX('H', 8, AF12)>,
+				 <STM32_PINMUX('H', 9, AF12)>,
+				 <STM32_PINMUX('H',10, AF12)>,
+				 <STM32_PINMUX('H',11, AF12)>,
+				 <STM32_PINMUX('H',12, AF12)>,
+				 <STM32_PINMUX('H',13, AF12)>,
+				 <STM32_PINMUX('H',14, AF12)>,
+				 <STM32_PINMUX('H',15, AF12)>,
+
+				 <STM32_PINMUX('I', 0, AF12)>,
+				 <STM32_PINMUX('I', 1, AF12)>,
+				 <STM32_PINMUX('I', 2, AF12)>,
+				 <STM32_PINMUX('I', 3, AF12)>,
+				 <STM32_PINMUX('I', 4, AF12)>,
+				 <STM32_PINMUX('I', 5, AF12)>,
+				 <STM32_PINMUX('I', 6, AF12)>,
+				 <STM32_PINMUX('I', 7, AF12)>,
+				 <STM32_PINMUX('I', 9, AF12)>,
+				 <STM32_PINMUX('I',10, AF12)>;
+
+			slew-rate = <3>;
+		};
+	};
+
+	pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 {
+		pins {
+			pinmux = <STM32_PINMUX('B', 8, AF7)>,
+				 <STM32_PINMUX('B', 9, AF7)>,
+				 <STM32_PINMUX('C', 6, AF8)>,
+				 <STM32_PINMUX('C', 7, AF8)>;
+			drive-push-pull;
+			slew-rate = <3>;
+		};
+	};
+
+	sdmmc1_pins: sdmmc@0 {
+		pins {
+			pinmux = <STM32_PINMUX('C', 8, AF12)>,
+				 <STM32_PINMUX('C', 9, AF12)>,
+				 <STM32_PINMUX('C',10, AF12)>,
+				 <STM32_PINMUX('C',11, AF12)>,
+				 <STM32_PINMUX('C',12, AF12)>,
+				 <STM32_PINMUX('D', 2, AF12)>;
+
+			slew-rate = <3>;
+			drive-push-pull;
+			bias-disable;
+		};
+	};
+};
+
+&pwrcfg {
+	u-boot,dm-pre-reloc;
+};
+
+&rcc {
+	u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/stm32h743-pinctrl.dtsi b/arch/arm/dts/stm32h743-pinctrl.dtsi
index e4f4aa579bd..c823541a0d8 100644
--- a/arch/arm/dts/stm32h743-pinctrl.dtsi
+++ b/arch/arm/dts/stm32h743-pinctrl.dtsi
@@ -40,234 +40,182 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include <dt-bindings/pinctrl/stm32h7-pinfunc.h>
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
 
 / {
 	soc {
-		pin-controller {
+		pinctrl: pin-controller {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "st,stm32h743-pinctrl";
 			ranges = <0 0x58020000 0x3000>;
+			interrupt-parent = <&exti>;
+			st,syscfg = <&syscfg 0x8>;
 			pins-are-numbered;
 
 			gpioa: gpio@58020000 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0x0 0x400>;
 				clocks = <&rcc GPIOA_CK>;
 				st,bank-name = "GPIOA";
+				interrupt-controller;
+				#interrupt-cells = <2>;
 			};
 
 			gpiob: gpio@58020400 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0x400 0x400>;
 				clocks = <&rcc GPIOB_CK>;
 				st,bank-name = "GPIOB";
+				interrupt-controller;
+				#interrupt-cells = <2>;
 			};
 
 			gpioc: gpio@58020800 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0x800 0x400>;
 				clocks = <&rcc GPIOC_CK>;
 				st,bank-name = "GPIOC";
+				interrupt-controller;
+				#interrupt-cells = <2>;
 			};
 
 			gpiod: gpio@58020c00 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0xc00 0x400>;
 				clocks = <&rcc GPIOD_CK>;
 				st,bank-name = "GPIOD";
+				interrupt-controller;
+				#interrupt-cells = <2>;
 			};
 
 			gpioe: gpio@58021000 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0x1000 0x400>;
 				clocks = <&rcc GPIOE_CK>;
 				st,bank-name = "GPIOE";
+				interrupt-controller;
+				#interrupt-cells = <2>;
 			};
 
 			gpiof: gpio@58021400 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0x1400 0x400>;
 				clocks = <&rcc GPIOF_CK>;
 				st,bank-name = "GPIOF";
+				interrupt-controller;
+				#interrupt-cells = <2>;
 			};
 
 			gpiog: gpio@58021800 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0x1800 0x400>;
 				clocks = <&rcc GPIOG_CK>;
 				st,bank-name = "GPIOG";
+				interrupt-controller;
+				#interrupt-cells = <2>;
 			};
 
 			gpioh: gpio@58021c00 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0x1c00 0x400>;
 				clocks = <&rcc GPIOH_CK>;
 				st,bank-name = "GPIOH";
+				interrupt-controller;
+				#interrupt-cells = <2>;
 			};
 
 			gpioi: gpio@58022000 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0x2000 0x400>;
 				clocks = <&rcc GPIOI_CK>;
 				st,bank-name = "GPIOI";
+				interrupt-controller;
+				#interrupt-cells = <2>;
 			};
 
 			gpioj: gpio@58022400 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0x2400 0x400>;
 				clocks = <&rcc GPIOJ_CK>;
 				st,bank-name = "GPIOJ";
+				interrupt-controller;
+				#interrupt-cells = <2>;
 			};
 
 			gpiok: gpio@58022800 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0x2800 0x400>;
 				clocks = <&rcc GPIOK_CK>;
 				st,bank-name = "GPIOK";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			i2c1_pins_a: i2c1@0 {
+				pins {
+					pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
+						 <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
+					bias-disable;
+					drive-open-drain;
+					slew-rate = <0>;
+				};
 			};
 
 			usart1_pins: usart1@0 {
 				pins1 {
-					pinmux = <STM32H7_PB14_FUNC_USART1_TX>;
+					pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
 					bias-disable;
 					drive-push-pull;
 					slew-rate = <0>;
 				};
 				pins2 {
-					pinmux = <STM32H7_PB15_FUNC_USART1_RX>;
+					pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
 					bias-disable;
 				};
 			};
 
 			usart2_pins: usart2@0 {
 				pins1 {
-					pinmux = <STM32H7_PD5_FUNC_USART2_TX>;
+					pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
 					bias-disable;
 					drive-push-pull;
 					slew-rate = <0>;
 				};
 				pins2 {
-					pinmux = <STM32H7_PD6_FUNC_USART2_RX>;
+					pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
 					bias-disable;
 				};
 			};
 
-			fmc_pins: fmc@0 {
-				  pins {
-					  pinmux = <STM32H7_PD0_FUNC_FMC_D2_FMC_DA2>,
-						  <STM32H7_PD1_FUNC_FMC_D3_FMC_DA3>,
-						  <STM32H7_PD8_FUNC_FMC_D13_FMC_DA13>,
-						  <STM32H7_PD9_FUNC_FMC_D14_FMC_DA14>,
-						  <STM32H7_PD10_FUNC_FMC_D15_FMC_DA15>,
-						  <STM32H7_PD14_FUNC_FMC_D0_FMC_DA0>,
-						  <STM32H7_PD15_FUNC_FMC_D1_FMC_DA1>,
-
-						  <STM32H7_PE0_FUNC_FMC_NBL0>,
-						  <STM32H7_PE1_FUNC_FMC_NBL1>,
-						  <STM32H7_PE7_FUNC_FMC_D4_FMC_DA4>,
-						  <STM32H7_PE8_FUNC_FMC_D5_FMC_DA5>,
-						  <STM32H7_PE9_FUNC_FMC_D6_FMC_DA6>,
-						  <STM32H7_PE10_FUNC_FMC_D7_FMC_DA7>,
-						  <STM32H7_PE11_FUNC_FMC_D8_FMC_DA8>,
-						  <STM32H7_PE12_FUNC_FMC_D9_FMC_DA9>,
-						  <STM32H7_PE13_FUNC_FMC_D10_FMC_DA10>,
-						  <STM32H7_PE14_FUNC_FMC_D11_FMC_DA11>,
-						  <STM32H7_PE15_FUNC_FMC_D12_FMC_DA12>,
-
-						  <STM32H7_PF0_FUNC_FMC_A0>,
-						  <STM32H7_PF1_FUNC_FMC_A1>,
-						  <STM32H7_PF2_FUNC_FMC_A2>,
-						  <STM32H7_PF3_FUNC_FMC_A3>,
-						  <STM32H7_PF4_FUNC_FMC_A4>,
-						  <STM32H7_PF5_FUNC_FMC_A5>,
-						  <STM32H7_PF11_FUNC_FMC_SDNRAS>,
-						  <STM32H7_PF12_FUNC_FMC_A6>,
-						  <STM32H7_PF13_FUNC_FMC_A7>,
-						  <STM32H7_PF14_FUNC_FMC_A8>,
-						  <STM32H7_PF15_FUNC_FMC_A9>,
-
-						  <STM32H7_PG0_FUNC_FMC_A10>,
-						  <STM32H7_PG1_FUNC_FMC_A11>,
-						  <STM32H7_PG2_FUNC_FMC_A12>,
-						  <STM32H7_PG4_FUNC_FMC_A14_FMC_BA0>,
-						  <STM32H7_PG5_FUNC_FMC_A15_FMC_BA1>,
-						  <STM32H7_PG8_FUNC_FMC_SDCLK>,
-						  <STM32H7_PG15_FUNC_FMC_SDNCAS>,
-
-						  <STM32H7_PH5_FUNC_FMC_SDNWE>,
-						  <STM32H7_PH6_FUNC_FMC_SDNE1>,
-						  <STM32H7_PH7_FUNC_FMC_SDCKE1>,
-						  <STM32H7_PH8_FUNC_FMC_D16>,
-						  <STM32H7_PH9_FUNC_FMC_D17>,
-						  <STM32H7_PH10_FUNC_FMC_D18>,
-						  <STM32H7_PH11_FUNC_FMC_D19>,
-						  <STM32H7_PH12_FUNC_FMC_D20>,
-						  <STM32H7_PH13_FUNC_FMC_D21>,
-						  <STM32H7_PH14_FUNC_FMC_D22>,
-						  <STM32H7_PH15_FUNC_FMC_D23>,
-
-						  <STM32H7_PI0_FUNC_FMC_D24>,
-						  <STM32H7_PI1_FUNC_FMC_D25>,
-						  <STM32H7_PI2_FUNC_FMC_D26>,
-						  <STM32H7_PI3_FUNC_FMC_D27>,
-						  <STM32H7_PI4_FUNC_FMC_NBL2>,
-						  <STM32H7_PI5_FUNC_FMC_NBL3>,
-						  <STM32H7_PI6_FUNC_FMC_D28>,
-						  <STM32H7_PI7_FUNC_FMC_D29>,
-						  <STM32H7_PI9_FUNC_FMC_D30>,
-						  <STM32H7_PI10_FUNC_FMC_D31>;
-
-					  slew-rate = <3>;
-				};
-			};
-
-			sdmmc1_pins: sdmmc@0 {
+			usbotg_hs_pins_a: usbotg-hs@0 {
 				pins {
-					pinmux = <STM32H7_PC8_FUNC_SDMMC1_D0>,
-						 <STM32H7_PC9_FUNC_SDMMC1_D1>,
-						 <STM32H7_PC10_FUNC_SDMMC1_D2>,
-						 <STM32H7_PC11_FUNC_SDMMC1_D3>,
-						 <STM32H7_PC12_FUNC_SDMMC1_CK>,
-						 <STM32H7_PD2_FUNC_SDMMC1_CMD>;
-
-					slew-rate = <3>;
-					drive-push-pull;
+					pinmux = <STM32_PINMUX('H', 4, AF10)>,	/* ULPI_NXT */
+							 <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
+							 <STM32_PINMUX('C', 0, AF10)>,	/* ULPI_STP> */
+							 <STM32_PINMUX('A', 5, AF10)>,	/* ULPI_CK> */
+							 <STM32_PINMUX('A', 3, AF10)>,	/* ULPI_D0> */
+							 <STM32_PINMUX('B', 0, AF10)>,	/* ULPI_D1> */
+							 <STM32_PINMUX('B', 1, AF10)>,	/* ULPI_D2> */
+							 <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
+							 <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
+							 <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
+							 <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
+							 <STM32_PINMUX('B', 5, AF10)>;	/* ULPI_D7> */
 					bias-disable;
-				};
-			};
-
-			pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 {
-				pins {
-					pinmux = <STM32H7_PB8_FUNC_SDMMC1_CKIN>,
-						 <STM32H7_PB9_FUNC_SDMMC1_CDIR>,
-						 <STM32H7_PC6_FUNC_SDMMC1_D0DIR>,
-						 <STM32H7_PC7_FUNC_SDMMC1_D123DIR>;
 					drive-push-pull;
-					slew-rate = <3>;
+					slew-rate = <2>;
 				};
 			};
 		};
diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi
index d5b8d879ee2..cbdd69ca9e7 100644
--- a/arch/arm/dts/stm32h743.dtsi
+++ b/arch/arm/dts/stm32h743.dtsi
@@ -44,13 +44,14 @@
 #include "armv7-m.dtsi"
 #include <dt-bindings/clock/stm32h7-clks.h>
 #include <dt-bindings/mfd/stm32h7-rcc.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
 	clocks {
 		clk_hse: clk-hse {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
-			clock-frequency = <25000000>;
+			clock-frequency = <0>;
 		};
 
 		clk_lse: clk-lse {
@@ -67,71 +68,448 @@
 	};
 
 	soc {
-		rcc: rcc@58024400 {
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-			compatible = "st,stm32h743-rcc", "st,stm32-rcc";
-			reg = <0x58024400 0x400>;
-			clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>, <&clk_hsi>, <&clk_csi>;
-			st,syscfg = <&pwrcfg>;
+		timer5: timer@40000c00 {
+			compatible = "st,stm32-timer";
+			reg = <0x40000c00 0x400>;
+			interrupts = <50>;
+			clocks = <&rcc TIM5_CK>;
 		};
 
-		usart1: serial@40011000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x40011000 0x400>;
-			interrupts = <37>;
+		lptimer1: timer@40002400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-lptimer";
+			reg = <0x40002400 0x400>;
+			clocks = <&rcc LPTIM1_CK>;
+			clock-names = "mux";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm-lp";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			trigger@0 {
+				compatible = "st,stm32-lptimer-trigger";
+				reg = <0>;
+				status = "disabled";
+			};
+
+			counter {
+				compatible = "st,stm32-lptimer-counter";
+				status = "disabled";
+			};
+		};
+
+		spi2: spi@40003800 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32h7-spi";
+			reg = <0x40003800 0x400>;
+			interrupts = <36>;
+			clocks = <&rcc SPI2_CK>;
+			status = "disabled";
+
+		};
+
+		spi3: spi@40003c00 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32h7-spi";
+			reg = <0x40003c00 0x400>;
+			interrupts = <51>;
+			clocks = <&rcc SPI3_CK>;
 			status = "disabled";
-			clocks = <&rcc USART1_CK>;
 		};
 
 		usart2: serial@40004400 {
-			compatible = "st,stm32h7-uart";
+			compatible = "st,stm32f7-uart";
 			reg = <0x40004400 0x400>;
 			interrupts = <38>;
 			status = "disabled";
 			clocks = <&rcc USART2_CK>;
 		};
 
-		timer5: timer@40000c00 {
-			compatible = "st,stm32-timer";
-			reg = <0x40000c00 0x400>;
-			interrupts = <50>;
-			clocks = <&rcc TIM5_CK>;
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32f7-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005400 0x400>;
+			interrupts = <31>,
+				     <32>;
+			resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
+			clocks = <&rcc I2C1_CK>;
+			status = "disabled";
 		};
 
-		pwrcfg: power-config@58024800 {
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32f7-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			interrupts = <33>,
+				     <34>;
+			resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
+			clocks = <&rcc I2C2_CK>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@40005C00 {
+			compatible = "st,stm32f7-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005C00 0x400>;
+			interrupts = <72>,
+				     <73>;
+			resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
+			clocks = <&rcc I2C3_CK>;
+			status = "disabled";
+		};
+
+		dac: dac@40007400 {
+			compatible = "st,stm32h7-dac-core";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc DAC12_CK>;
+			clock-names = "pclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			dac1: dac@1 {
+				compatible = "st,stm32-dac";
+				#io-channels-cells = <1>;
+				reg = <1>;
+				status = "disabled";
+			};
+
+			dac2: dac@2 {
+				compatible = "st,stm32-dac";
+				#io-channels-cells = <1>;
+				reg = <2>;
+				status = "disabled";
+			};
+		};
+
+		usart1: serial@40011000 {
+			compatible = "st,stm32f7-uart";
+			reg = <0x40011000 0x400>;
+			interrupts = <37>;
+			status = "disabled";
+			clocks = <&rcc USART1_CK>;
+		};
+
+		spi1: spi@40013000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32h7-spi";
+			reg = <0x40013000 0x400>;
+			interrupts = <35>;
+			clocks = <&rcc SPI1_CK>;
+			status = "disabled";
+		};
+
+		spi4: spi@40013400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32h7-spi";
+			reg = <0x40013400 0x400>;
+			interrupts = <84>;
+			clocks = <&rcc SPI4_CK>;
+			status = "disabled";
+		};
+
+		spi5: spi@40015000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32h7-spi";
+			reg = <0x40015000 0x400>;
+			interrupts = <85>;
+			clocks = <&rcc SPI5_CK>;
+			status = "disabled";
+		};
+
+		dma1: dma@40020000 {
+			compatible = "st,stm32-dma";
+			reg = <0x40020000 0x400>;
+			interrupts = <11>,
+				     <12>,
+				     <13>,
+				     <14>,
+				     <15>,
+				     <16>,
+				     <17>,
+				     <47>;
+			clocks = <&rcc DMA1_CK>;
+			#dma-cells = <4>;
+			st,mem2mem;
+			dma-requests = <8>;
+			status = "disabled";
+		};
+
+		dma2: dma@40020400 {
+			compatible = "st,stm32-dma";
+			reg = <0x40020400 0x400>;
+			interrupts = <56>,
+				     <57>,
+				     <58>,
+				     <59>,
+				     <60>,
+				     <68>,
+				     <69>,
+				     <70>;
+			clocks = <&rcc DMA2_CK>;
+			#dma-cells = <4>;
+			st,mem2mem;
+			dma-requests = <8>;
+			status = "disabled";
+		};
+
+		dmamux1: dma-router@40020800 {
+			compatible = "st,stm32h7-dmamux";
+			reg = <0x40020800 0x1c>;
+			#dma-cells = <3>;
+			dma-channels = <16>;
+			dma-requests = <128>;
+			dma-masters = <&dma1 &dma2>;
+			clocks = <&rcc DMA1_CK>;
+		};
+
+		adc_12: adc@40022000 {
+			compatible = "st,stm32h7-adc-core";
+			reg = <0x40022000 0x400>;
+			interrupts = <18>;
+			clocks = <&rcc ADC12_CK>;
+			clock-names = "bus";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			adc1: adc@0 {
+				compatible = "st,stm32h7-adc";
+				#io-channel-cells = <1>;
+				reg = <0x0>;
+				interrupt-parent = <&adc_12>;
+				interrupts = <0>;
+				status = "disabled";
+			};
+
+			adc2: adc@100 {
+				compatible = "st,stm32h7-adc";
+				#io-channel-cells = <1>;
+				reg = <0x100>;
+				interrupt-parent = <&adc_12>;
+				interrupts = <1>;
+				status = "disabled";
+			};
+		};
+
+		usbotg_hs: usb@40040000 {
+			compatible = "st,stm32f7-hsotg";
+			reg = <0x40040000 0x40000>;
+			interrupts = <77>;
+			clocks = <&rcc USB1OTG_CK>;
+			clock-names = "otg";
+			g-rx-fifo-size = <256>;
+			g-np-tx-fifo-size = <32>;
+			g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
+			status = "disabled";
+		};
+
+		usbotg_fs: usb@40080000 {
+			compatible = "st,stm32f4x9-fsotg";
+			reg = <0x40080000 0x40000>;
+			interrupts = <101>;
+			clocks = <&rcc USB2OTG_CK>;
+			clock-names = "otg";
+			status = "disabled";
+		};
+
+		mdma1: dma@52000000 {
+			compatible = "st,stm32h7-mdma";
+			reg = <0x52000000 0x1000>;
+			interrupts = <122>;
+			clocks = <&rcc MDMA_CK>;
+			#dma-cells = <5>;
+			dma-channels = <16>;
+			dma-requests = <32>;
+		};
+
+		exti: interrupt-controller@58000000 {
+			compatible = "st,stm32h7-exti";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x58000000 0x400>;
+			interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
+		};
+
+		syscfg: system-config@58000400 {
 			compatible = "syscon";
-			reg = <0x58024800 0x400>;
+			reg = <0x58000400 0x400>;
 		};
 
-		fmc: fmc@52004000 {
-			compatible = "st,stm32h7-fmc";
-			reg = <0x52004000 0x1000>;
-			clocks = <&rcc FMC_CK>;
+		spi6: spi@58001400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32h7-spi";
+			reg = <0x58001400 0x400>;
+			interrupts = <86>;
+			clocks = <&rcc SPI6_CK>;
+			status = "disabled";
 		};
 
-		clk_hsi: clk-hsi {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <64000000>;
+		i2c4: i2c@58001C00 {
+			compatible = "st,stm32f7-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58001C00 0x400>;
+			interrupts = <95>,
+				     <96>;
+			resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
+			clocks = <&rcc I2C4_CK>;
+			status = "disabled";
 		};
 
-		clk_csi: clk-csi {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <4000000>;
+		lptimer2: timer@58002400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-lptimer";
+			reg = <0x58002400 0x400>;
+			clocks = <&rcc LPTIM2_CK>;
+			clock-names = "mux";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm-lp";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			trigger@1 {
+				compatible = "st,stm32-lptimer-trigger";
+				reg = <1>;
+				status = "disabled";
+			};
+
+			counter {
+				compatible = "st,stm32-lptimer-counter";
+				status = "disabled";
+			};
+		};
+
+		lptimer3: timer@58002800 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-lptimer";
+			reg = <0x58002800 0x400>;
+			clocks = <&rcc LPTIM3_CK>;
+			clock-names = "mux";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm-lp";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			trigger@2 {
+				compatible = "st,stm32-lptimer-trigger";
+				reg = <2>;
+				status = "disabled";
+			};
+		};
+
+		lptimer4: timer@58002c00 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-lptimer";
+			reg = <0x58002c00 0x400>;
+			clocks = <&rcc LPTIM4_CK>;
+			clock-names = "mux";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm-lp";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
 		};
 
-		sdmmc1: sdmmc@52007000 {
-			compatible = "st,stm32-sdmmc2";
-			reg = <0x52007000 0x1000>;
-			interrupts = <49>;
-			clocks = <&rcc SDMMC1_CK>;
-			resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
-			st,idma = <1>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
+		lptimer5: timer@58003000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-lptimer";
+			reg = <0x58003000 0x400>;
+			clocks = <&rcc LPTIM5_CK>;
+			clock-names = "mux";
 			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm-lp";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+		};
+
+		vrefbuf: regulator@58003c00 {
+			compatible = "st,stm32-vrefbuf";
+			reg = <0x58003C00 0x8>;
+			clocks = <&rcc VREF_CK>;
+			regulator-min-microvolt = <1500000>;
+			regulator-max-microvolt = <2500000>;
+			status = "disabled";
+		};
+
+		rtc: rtc@58004000 {
+			compatible = "st,stm32h7-rtc";
+			reg = <0x58004000 0x400>;
+			clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
+			clock-names = "pclk", "rtc_ck";
+			assigned-clocks = <&rcc RTC_CK>;
+			assigned-clock-parents = <&rcc LSE_CK>;
+			interrupt-parent = <&exti>;
+			interrupts = <17 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "alarm";
+			st,syscfg = <&pwrcfg 0x00 0x100>;
+			status = "disabled";
+		};
+
+		rcc: reset-clock-controller@58024400 {
+			compatible = "st,stm32h743-rcc", "st,stm32-rcc";
+			reg = <0x58024400 0x400>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
+			st,syscfg = <&pwrcfg>;
+		};
+
+		pwrcfg: power-config@58024800 {
+			compatible = "syscon";
+			reg = <0x58024800 0x400>;
+		};
+
+		adc_3: adc@58026000 {
+			compatible = "st,stm32h7-adc-core";
+			reg = <0x58026000 0x400>;
+			interrupts = <127>;
+			clocks = <&rcc ADC3_CK>;
+			clock-names = "bus";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			adc3: adc@0 {
+				compatible = "st,stm32h7-adc";
+				#io-channel-cells = <1>;
+				reg = <0x0>;
+				interrupt-parent = <&adc_3>;
+				interrupts = <0>;
+				status = "disabled";
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/stm32h743i-disco-u-boot.dtsi b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
new file mode 100644
index 00000000000..2d6b41bfb96
--- /dev/null
+++ b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <stm32h7-u-boot.dtsi>
+
+&sdmmc1 {
+	status = "okay";
+	pinctrl-0 = <&sdmmc1_pins>;
+	pinctrl-names = "default";
+	bus-width = <4>;
+	cd-gpios = <&gpioi 8 1>;
+};
diff --git a/arch/arm/dts/stm32h743i-disco.dts b/arch/arm/dts/stm32h743i-disco.dts
index 917a859a09f..45e088c5574 100644
--- a/arch/arm/dts/stm32h743i-disco.dts
+++ b/arch/arm/dts/stm32h743i-disco.dts
@@ -43,7 +43,6 @@
 /dts-v1/;
 #include "stm32h743.dtsi"
 #include "stm32h743-pinctrl.dtsi"
-#include <dt-bindings/memory/stm32-sdram.h>
 
 / {
 	model = "STMicroelectronics STM32H743i-Discovery board";
@@ -60,50 +59,15 @@
 
 	aliases {
 		serial0 = &usart2;
-		mmc0 = &sdmmc1;
-		gpio0 = &gpioa;
-		gpio1 = &gpiob;
-		gpio2 = &gpioc;
-		gpio3 = &gpiod;
-		gpio4 = &gpioe;
-		gpio5 = &gpiof;
-		gpio6 = &gpiog;
-		gpio7 = &gpioh;
-		gpio8 = &gpioi;
-		gpio9 = &gpioj;
-		gpio10 = &gpiok;
 	};
 };
 
-&usart2 {
-	pinctrl-0 = <&usart2_pins>;
-	pinctrl-names = "default";
-	status = "okay";
+&clk_hse {
+	clock-frequency = <25000000>;
 };
 
-&fmc {
-	pinctrl-0 = <&fmc_pins>;
+&usart2 {
+	pinctrl-0 = <&usart2_pins>;
 	pinctrl-names = "default";
 	status = "okay";
-
-	/*
-	 * Memory configuration from sdram datasheet IS42S32800G-6BLI
-	 * firsct bank is bank@0
-	 * second bank is bank@1
-	 */
-	bank1: bank@1 {
-		st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
-				  CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
-		st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
-				  TWR_1 TRCD_1>;
-		st,sdram-refcount = <1539>;
-	};
-};
-
-&sdmmc1 {
-	status = "okay";
-	pinctrl-0 = <&sdmmc1_pins>;
-	pinctrl-names = "default";
-	bus-width = <4>;
-	cd-gpios = <&gpioi 8 1>;
 };
diff --git a/arch/arm/dts/stm32h743i-eval-u-boot.dtsi b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi
new file mode 100644
index 00000000000..251977abe02
--- /dev/null
+++ b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <stm32h7-u-boot.dtsi>
+
+&sdmmc1 {
+	status = "okay";
+	pinctrl-0 = <&sdmmc1_pins>,
+		    <&pinctrl_sdmmc1_level_shifter>;
+	pinctrl-names = "default";
+	bus-width = <4>;
+	st,sig-dir;
+};
diff --git a/arch/arm/dts/stm32h743i-eval.dts b/arch/arm/dts/stm32h743i-eval.dts
index 28c876be27f..3f8e0c4a998 100644
--- a/arch/arm/dts/stm32h743i-eval.dts
+++ b/arch/arm/dts/stm32h743i-eval.dts
@@ -43,7 +43,6 @@
 /dts-v1/;
 #include "stm32h743.dtsi"
 #include "stm32h743-pinctrl.dtsi"
-#include <dt-bindings/memory/stm32-sdram.h>
 
 / {
 	model = "STMicroelectronics STM32H743i-EVAL board";
@@ -60,50 +59,62 @@
 
 	aliases {
 		serial0 = &usart1;
-		gpio0 = &gpioa;
-		gpio1 = &gpiob;
-		gpio2 = &gpioc;
-		gpio3 = &gpiod;
-		gpio4 = &gpioe;
-		gpio5 = &gpiof;
-		gpio6 = &gpiog;
-		gpio7 = &gpioh;
-		gpio8 = &gpioi;
-		gpio9 = &gpioj;
-		gpio10 = &gpiok;
 	};
+
+	vdda: regulator-vdda {
+		compatible = "regulator-fixed";
+		regulator-name = "vdda";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	usbotg_hs_phy: usb-phy {
+		#phy-cells = <0>;
+		compatible = "usb-nop-xceiv";
+		clocks = <&rcc USB1ULPI_CK>;
+		clock-names = "main_clk";
+	};
+
 };
 
-&usart1 {
-	pinctrl-0 = <&usart1_pins>;
-	pinctrl-names = "default";
+&adc_12 {
+	vref-supply = <&vdda>;
 	status = "okay";
+	adc1: adc@0 {
+		/* potentiometer */
+		st,adc-channels = <0>;
+		status = "okay";
+	};
+};
+
+&clk_hse {
+	clock-frequency = <25000000>;
 };
 
-&fmc {
-	pinctrl-0 = <&fmc_pins>;
+&i2c1 {
+	pinctrl-0 = <&i2c1_pins_a>;
 	pinctrl-names = "default";
+	i2c-scl-rising-time-ns = <185>;
+	i2c-scl-falling-time-ns = <20>;
 	status = "okay";
+};
 
-	/*
-	 * Memory configuration from sdram datasheet IS42S32800G-6BLI
-	 * firsct bank is bank@0
-	 * second bank is bank@1
-	 */
-	bank2: bank@1 {
-		st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
-				  CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
-		st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
-				  TWR_1 TRCD_1>;
-		st,sdram-refcount = <1539>;
-	};
+&rtc {
+	status = "okay";
 };
 
-&sdmmc1 {
+&usart1 {
+	pinctrl-0 = <&usart1_pins>;
+	pinctrl-names = "default";
 	status = "okay";
-	pinctrl-0 = <&sdmmc1_pins>,
-		    <&pinctrl_sdmmc1_level_shifter>;
+};
+
+&usbotg_hs {
+	pinctrl-0 = <&usbotg_hs_pins_a>;
 	pinctrl-names = "default";
-	bus-width = <4>;
-	st,dirpol;
+	phys = <&usbotg_hs_phy>;
+	phy-names = "usb2-phy";
+	dr_mode = "otg";
+	status = "okay";
 };
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
index 0366782fda9..b10208f6987 100644
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -342,9 +342,9 @@
 &sdmmc1 {
 	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
 	broken-cd;
-	st,dirpol;
-	st,negedge;
-	st,pin-ckin;
+	st,sig-dir;
+	st,neg-edge;
+	st,use-ckin;
 	bus-width = <4>;
 	vmmc-supply = <&vdd_sd>;
 	vqmmc-supply = <&sd_switch>;
@@ -361,8 +361,8 @@
 	non-removable;
 	no-sd;
 	no-sdio;
-	st,dirpol;
-	st,negedge;
+	st,sig-dir;
+	st,neg-edge;
 	bus-width = <8>;
 	vmmc-supply = <&v3v3>;
 	vqmmc-supply = <&vdd>;
author	Tom Rini	2019-04-24 12:26:39 -0400
committer	Tom Rini	2019-04-24 12:26:39 -0400
commit	c2bb9c5b9e333c200e3702d9ed5ac9b6095191b6 (patch)
tree	f3a017fe861211d45c8965aeac2f488f06c989d5 /arch/arm
parent	ceb6ddbc73607e9395bb5f0ad94159755f049e77 (diff)
parent	c406a474311c1ee3c4303a7e85db4a8e45966e31 (diff)