diff options
| author | Lokesh Vutla | 2018-08-27 15:57:10 +0530 |
|---|---|---|
| committer | Tom Rini | 2018-09-11 08:32:55 -0400 |
| commit | f70b72e3533a135d159b182f8037993c802f1853 (patch) | |
| tree | bf270b7f12a24a58f005c6c7739ea5f8bafeee80 /arch/arm | |
| parent | ed0e60512407716d17405e45e12c92e52918608a (diff) | |
arm: K3: Update _start instruction
On K3 family SoCs, once the ROM loads image on R5, M3 resets R5 and
expects to start executing from 0x0. In order to handle this ROM
updates the boot vector of R5 such that first 64 bytes of image load
address are mapped to 0x0.
In this case, it is SPL's responsibility to jump to the proper image
location. So, update the PC with address of reset vector(like how
other exception vectors are handled), instead of branching to reset.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/lib/vectors.S | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index d629cb1dc2d..2ca6e2494a7 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -19,7 +19,11 @@ * for the non-boot0 case or by a boot0-header. */ .macro ARM_VECTORS +#ifdef CONFIG_ARCH_K3 + ldr pc, _reset +#else b reset +#endif ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -94,6 +98,7 @@ _start: ************************************************************************* */ + .globl _reset .globl _undefined_instruction .globl _software_interrupt .globl _prefetch_abort @@ -102,6 +107,9 @@ _start: .globl _irq .globl _fiq +#ifdef CONFIG_ARCH_K3 +_reset: .word reset +#endif _undefined_instruction: .word undefined_instruction _software_interrupt: .word software_interrupt _prefetch_abort: .word prefetch_abort |