diff options
| author | Sonic Zhang | 2013-02-05 18:57:49 +0800 |
|---|---|---|
| committer | Sonic Zhang | 2013-05-13 15:47:24 +0800 |
| commit | f4d8038439fb372c91c3a27121a911c359603bcf (patch) | |
| tree | c9a576f2f81d7ad65d8222f20f5c4a1fc4fa0e24 /arch/blackfin/cpu | |
| parent | ddb5c5be1eddd38a47dc197cfacdbf149930740d (diff) | |
blackfin: run core1 from L1 code sram start address in uboot init code on core 0
Define core 1 L1 code sram start address.
Add function to enable core 1 for BF609 and BF561.
Add config macro to allow customer to run core 1 in uboot init code on core 0.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Diffstat (limited to 'arch/blackfin/cpu')
| -rw-r--r-- | arch/blackfin/cpu/cpu.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c index 0be2e2b835b..d841f64c82c 100644 --- a/arch/blackfin/cpu/cpu.c +++ b/arch/blackfin/cpu/cpu.c @@ -23,6 +23,32 @@ ulong bfin_poweron_retx; +#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START) +void bfin_core1_start(void) +{ +#ifdef BF561_FAMILY + /* Enable core 1 */ + bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020); +#else + /* Enable core 1 */ + bfin_write32(RCU0_SVECT1, COREB_L1_CODE_START); + bfin_write32(RCU0_CRCTL, 0); + + bfin_write32(RCU0_CRCTL, 0x2); + + /* Check if core 1 starts */ + while (!(bfin_read32(RCU0_CRSTAT) & 0x2)) + continue; + + bfin_write32(RCU0_CRCTL, 0); + + /* flag to notify cces core 1 application */ + bfin_write32(SDU0_MSG_SET, (1 << 19)); +#endif +} +#endif + +__attribute__ ((__noreturn__)) void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) { #ifndef CONFIG_BFIN_BOOTROM_USES_EVT1 @@ -72,6 +98,10 @@ void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) # endif #endif +#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START) + bfin_core1_start(); +#endif + serial_early_puts("Board init flash\n"); board_init_f(bootflag); } |