diff options
| author | Paul Burton | 2016-09-21 11:18:57 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck | 2016-09-21 15:04:04 +0200 |
| commit | c5b8412d60e22b49348a63848cbf7b6ab5ccb16e (patch) | |
| tree | d5d8f1617c60ce1f6da776e871943c36cadd7043 /arch/mips/cpu | |
| parent | 566ce04de4a2b4c66be8e13751dbb0bfe80117b3 (diff) | |
MIPS: Ensure Config.K0=2 applies before any memory accesses
During boot we set Config.K0=2 (uncached) such that any accesses to the
kseg0 memory region are performed uncached before the caches are
initialised. This write to the Config register introduces an execution
hazard between it & any following memory accesses (such as the load of
_gp), which we need to clear in order to ensure those memory accesses
are actually performed uncached. Clear this execution hazard with the
insertion of an ehb execution hazard barrier instruction.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat (limited to 'arch/mips/cpu')
| -rw-r--r-- | arch/mips/cpu/start.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index c157d03d314..8f85ede9ad2 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -127,6 +127,7 @@ reset: and t0, t0, MIPS_CONF_IMPL or t0, t0, CONF_CM_UNCACHED mtc0 t0, CP0_CONFIG + ehb #endif /* |