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authorStefan Roese2018-08-16 15:27:30 +0200
committerDaniel Schwierzeck2018-09-23 14:27:19 +0200
commitb02f76a83541fe9fe3a2918039b26fc133699c17 (patch)
treeff188bc459ac530efff25495694432427741b682 /arch/mips/dts/linkit-smart-7688.dts
parent4c835a607bd5adf88a726c0f636b00dd31e50237 (diff)
mips: Add LinkIt Smart 7688 support
The LinkIt Smart 7688 modules have a MT7688 SoC with 128 MiB of RAM and 32 MiB of flash (SPI NOR). This patch also includes 2 targets. One is the target that can be programmed into the SPI NOR flash and a 2nd target "xxx-ram" is added to support loading and booting via an already running U-Boot version. This allows easy development and testing without the need to flash the image each time. Signed-off-by: Stefan Roese <sr@denx.de> [fixed and regenerated defconfig files] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'arch/mips/dts/linkit-smart-7688.dts')
-rw-r--r--arch/mips/dts/linkit-smart-7688.dts46
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/mips/dts/linkit-smart-7688.dts b/arch/mips/dts/linkit-smart-7688.dts
new file mode 100644
index 00000000000..df4bf907c6b
--- /dev/null
+++ b/arch/mips/dts/linkit-smart-7688.dts
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>
+ */
+
+/dts-v1/;
+
+#include "mt7628a.dtsi"
+
+/ {
+ compatible = "seeed,linkit-smart-7688", "ralink,mt7628a-soc";
+ model = "LinkIt-Smart-7688";
+
+ aliases {
+ serial0 = &uart2;
+ spi0 = &spi0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,57600";
+ stdout-path = &uart2;
+ };
+};
+
+&uart2 {
+ status = "okay";
+ clock-frequency = <40000000>;
+};
+
+&spi0 {
+ status = "okay";
+ num-cs = <2>;
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash", "jedec,spi-nor";
+ spi-max-frequency = <25000000>;
+ reg = <0>;
+ };
+};